diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index d0f51e6d..8aa64112 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -10,7 +10,7 @@ case object BtbKey extends Field[BtbParameters]
 case class BtbParameters(nEntries: Int = 62, nRAS: Int = 2, updatesOutOfOrder: Boolean = false)
 
 abstract trait HasBtbParameters extends HasCoreParameters {
-  val matchBits = p(PgIdxBits)
+  val matchBits = pgIdxBits
   val entries = p(BtbKey).nEntries
   val nRAS = p(BtbKey).nRAS
   val updatesOutOfOrder = p(BtbKey).updatesOutOfOrder
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 6ff5a414..6f084aac 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -22,17 +22,9 @@ case object CoreDataBits extends Field[Int]
 case object CoreDCacheReqTagBits extends Field[Int]
 case object NCustomMRWCSRs extends Field[Int]
 
-trait HasCoreParameters {
+trait HasCoreParameters extends HasAddrMapParameters {
   implicit val p: Parameters
   val xLen = p(XLen)
-  val paddrBits = p(PAddrBits)
-  val vaddrBits = p(VAddrBits)
-  val pgIdxBits = p(PgIdxBits)
-  val ppnBits = p(PPNBits)
-  val vpnBits = p(VPNBits)
-  val pgLevels = p(PgLevels)
-  val pgLevelBits = p(PgLevelBits)
-  val asIdBits = p(ASIdBits)
 
   val retireWidth = p(RetireWidth)
   val fetchWidth = p(FetchWidth)
diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index 799c869b..eb6b72ce 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -9,8 +9,7 @@ import scala.math._
 
 case object NTLBEntries extends Field[Int]
 
-trait HasTLBParameters extends HasCoreParameters {
-  val addrMap = new AddrHashMap(p(NastiAddrMap))
+trait HasTLBParameters extends HasAddrMapParameters {
   val entries = p(NTLBEntries)
   val camAddrBits = ceil(log(entries)/log(2)).toInt
   val camTagBits = asIdBits + vpnBits