riscv/rocket-chip
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added HasAddrMapParameters

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This commit is contained in:
Henry Cook
2015-10-06 18:20:19 -07:00
parent 84576650b5
commit 8173695800
3 changed files with 3 additions and 12 deletions
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3
rocket/src/main/scala/tlb.scala
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@ -9,8 +9,7 @@ import scala.math._
case object NTLBEntries extends Field[Int]
trait HasTLBParameters extends HasCoreParameters {
val addrMap = new AddrHashMap(p(NastiAddrMap))
trait HasTLBParameters extends HasAddrMapParameters {
val entries = p(NTLBEntries)
val camAddrBits = ceil(log(entries)/log(2)).toInt
val camTagBits = asIdBits + vpnBits