riscv/rocket-chip
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added HasAddrMapParameters

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Henry Cook committed 2015-10-06 18:22:40 -07:00
1 parent 84576650b5
commit 8173695800
3 files changed
+3 -12
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rocket/src/main/scala/rocket.scala
+1 -9
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@@ -22,17 +22,9 @@ case object CoreDataBits extends Field[Int]
case object CoreDCacheReqTagBits extends Field[Int]
case object NCustomMRWCSRs extends Field[Int]
trait HasCoreParameters {
trait HasCoreParameters extends HasAddrMapParameters {
implicit val p: Parameters
val xLen = p(XLen)
val paddrBits = p(PAddrBits)
val vaddrBits = p(VAddrBits)
val pgIdxBits = p(PgIdxBits)
val ppnBits = p(PPNBits)
val vpnBits = p(VPNBits)
val pgLevels = p(PgLevels)
val pgLevelBits = p(PgLevelBits)
val asIdBits = p(ASIdBits)
val retireWidth = p(RetireWidth)
val fetchWidth = p(FetchWidth)