riscv/rocket-chip
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Ported FPU parameters to new Chisel Parameters

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Adam Izraelevitz authored and Henry Cook committed 2014-08-19 11:37:27 -07:00
1 parent 4ac8e59b1f
commit 812353bace
5 files changed
+18 -15
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rocket/src/main/scala/tile.scala
-1
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@@ -6,7 +6,6 @@ import Util._
case class RocketConfiguration(tl: TileLinkConfiguration, as: AddressSpaceConfiguration,
icache: ICacheConfig, dcache: DCacheConfig,
fpu: Option[FPUConfig] = None,
rocc: Option[RocketConfiguration => RoCC] = None,
retireWidth: Int = 1,
vm: Boolean = true,