Ported FPU parameters to new Chisel Parameters

2014-08-01 18:01:08 -07:00
parent 4ac8e59b1f
commit 812353bace
5 changed files with 18 additions and 15 deletions
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@ -6,7 +6,6 @@ import Util._

 case class RocketConfiguration(tl: TileLinkConfiguration, as: AddressSpaceConfiguration,
                               icache: ICacheConfig, dcache: DCacheConfig,
-                               fpu: Option[FPUConfig] = None,
                               rocc: Option[RocketConfiguration => RoCC] = None,
                               retireWidth: Int = 1,
                               vm: Boolean = true,