riscv/rocket-chip
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Ported FPU parameters to new Chisel Parameters

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This commit is contained in:
Adam Izraelevitz
2014-08-01 18:01:08 -07:00
committed by Henry Cook
parent 4ac8e59b1f
commit 812353bace
5 changed files with 18 additions and 15 deletions
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8
rocket/src/main/scala/ctrl.scala
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@ -316,7 +316,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
}
var decode_table = XDecode.table
if (!conf.fpu.isEmpty) decode_table ++= FDecode.table
if (!params(HasFPU)) decode_table ++= FDecode.table
if (!conf.rocc.isEmpty) decode_table ++= RoCCDecode.table
val cs = DecodeLogic(io.dpath.inst, XDecode.decode_default, decode_table)
@ -411,13 +411,13 @@ class Control(implicit conf: RocketConfiguration) extends Module
val fp_csrs = CSRs.fcsr :: CSRs.frm :: CSRs.fflags :: Nil
val legal_csrs = collection.mutable.LinkedHashSet(CSRs.all:_*)
if (conf.fpu.isEmpty)
if (params(HasFPU))
legal_csrs --= fp_csrs
val id_csr_addr = io.dpath.inst(31,20)
val isLegalCSR = Vec.tabulate(1 << id_csr_addr.getWidth)(i => Bool(legal_csrs contains i))
val id_csr_en = id_csr != CSR.N
val id_csr_fp = Bool(!conf.fpu.isEmpty) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs)
val id_csr_fp = Bool(!params(HasFPU)) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs)
val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr)
val id_csr_invalid = id_csr_en && !isLegalCSR(id_csr_addr)
val id_csr_privileged = id_csr_en &&
@ -623,7 +623,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
val sboard = new Scoreboard(32)
sboard.clear(io.dpath.ll_wen, io.dpath.ll_waddr)
val id_stall_fpu = if (!conf.fpu.isEmpty) {
val id_stall_fpu = if (!params(HasFPU)) {
val fp_sboard = new Scoreboard(32)
fp_sboard.set((wb_dcache_miss && wb_reg_fp_wen || io.fpu.sboard_set) && !replay_wb, io.dpath.wb_waddr)
fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra)