riscv/rocket-chip
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Ported FPU parameters to new Chisel Parameters

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This commit is contained in:
Adam Izraelevitz
2014-08-01 18:01:08 -07:00
committed by Henry Cook
parent 4ac8e59b1f
commit 812353bace
5 changed files with 18 additions and 15 deletions
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7
rocket/src/main/scala/core.scala
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@ -4,6 +4,9 @@ import Chisel._
import Util._
import uncore.HTIFIO
case object FPUParams extends Field[PF]
case object HasFPU extends Field[Boolean]
class RocketIO(implicit conf: RocketConfiguration) extends Bundle
{
val host = new HTIFIO(conf.tl.ln.nClients)
@ -20,8 +23,8 @@ class Core(implicit conf: RocketConfiguration) extends Module
val ctrl = Module(new Control)
val dpath = Module(new Datapath)
if (!conf.fpu.isEmpty) {
val fpu = Module(new FPU(conf.fpu.get))
if (!params(HasFPU)) {
val fpu = Module(new FPU,params(FPUParams))
dpath.io.fpu <> fpu.io.dpath
ctrl.io.fpu <> fpu.io.ctrl
}