fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
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@ -79,8 +79,7 @@ object Constants
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val WB_PC = UFix(0, 3);
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val WB_ALU = UFix(1, 3);
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val WB_PCR = UFix(2, 3);
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val WB_CR = UFix(3, 3);
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val WB_MUL = UFix(4, 3);
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val WB_TSC = UFix(3, 3);
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val N = UFix(0, 1);
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val Y = UFix(1, 1);
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@ -252,7 +252,8 @@ class rocketCtrl extends Component
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FENCE_I-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_I,N,N,N),
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CFLUSH-> List(Y, BR_N, REN_Y,REN_N,A2_X, A1_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,Y),
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MFPCR-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PCR,REN_Y,WEN_N,I_X ,SYNC_N,N,N,Y),
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MTPCR-> List(Y, BR_N, REN_N,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_Y,I_X ,SYNC_N,N,N,Y)
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MTPCR-> List(Y, BR_N, REN_N,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_Y,I_X ,SYNC_N,N,N,Y),
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RDTIME-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N)
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// Instructions that have not yet been implemented
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/*
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@ -303,9 +303,12 @@ class rocketDCacheDM(lines: Int) extends Component {
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p_store_valid <== Bool(false);
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db_array <== db_array.bitSet(p_store_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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when (resolve_store || (state === s_write_amo)) {
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when (resolve_store) {
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db_array <== db_array.bitSet(p_store_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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when (state === s_write_amo) {
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db_array <== db_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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when (tag_we) {
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db_array <== db_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(0,1));
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}
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@ -357,7 +360,7 @@ class rocketDCacheDM(lines: Int) extends Component {
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amo_alu.io.wmask := amo_wmask;
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amo_alu.io.lhs := Mux(r_cpu_resp_val, resp_data, r_resp_data).toUFix;
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amo_alu.io.rhs := r_amo_data.toUFix;
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val amo_alu_out = amo_alu.io.result;
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val amo_alu_out = Cat(amo_alu.io.result,amo_alu.io.result);
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data_array.io.a :=
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Mux(drain_store || resolve_store, p_store_idx(PGIDX_BITS-1, offsetmsb-1),
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@ -515,4 +518,4 @@ class rocketDCacheAmoALU extends Component {
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io.result := alu_out;
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}
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}
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}
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@ -370,13 +370,18 @@ class rocketDpath extends Component
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(~(ex_reg_rs1(63) ^ ex_reg_rs2(63)) & io.ctrl.br_ltu |
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ex_reg_rs1(63) & ~ex_reg_rs2(63)).toBool;
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// time stamp counter
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val tsc_reg = Reg(resetVal = UFix(0,64));
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tsc_reg <== tsc_reg + UFix(1);
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// writeback select mux
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ex_wdata :=
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Mux(ex_reg_ctrl_ll_wb || ex_reg_ctrl_wen_pcr, ex_reg_rs1,
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Mux(ex_reg_ctrl_sel_wb === WB_PC, Cat(Fill(64-VADDR_BITS, ex_reg_pc_plus4(VADDR_BITS-1)), ex_reg_pc_plus4),
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Mux(ex_reg_ctrl_sel_wb === WB_ALU, ex_alu_out,
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Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
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Bits(0, 64))))).toBits;
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Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg,
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Bits(0, 64)))))).toBits;
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// memory stage
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mem_reg_pc <== ex_reg_pc;
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