diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala
index d27d1003..4d28d5aa 100644
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@@ -79,8 +79,7 @@ object Constants
   val WB_PC  = UFix(0, 3);
   val WB_ALU = UFix(1, 3);
   val WB_PCR = UFix(2, 3);
-  val WB_CR  = UFix(3, 3);
-  val WB_MUL = UFix(4, 3);
+  val WB_TSC = UFix(3, 3);
 
   val N = UFix(0, 1);
   val Y = UFix(1, 1);
diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index d1adf6dd..a317785e 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -252,7 +252,8 @@ class rocketCtrl extends Component
       FENCE_I->  List(Y,     BR_N,  REN_N,REN_N,A2_X,    A1_X,  DW_X,  FN_X,   M_N,M_X,      MT_X, N,MUL_X,     N,DIV_X,    WEN_N,WA_X, WB_X,  REN_N,WEN_N,I_X ,SYNC_I,N,N,N),
       CFLUSH->   List(Y,     BR_N,  REN_Y,REN_N,A2_X,    A1_X,  DW_X,  FN_X,   M_Y,M_FLA,    MT_X, N,MUL_X,     N,DIV_X,    WEN_N,WA_X, WB_X,  REN_N,WEN_N,I_X ,SYNC_N,N,N,Y),
       MFPCR->    List(Y,     BR_N,  REN_N,REN_N,A2_X,    A1_X,  DW_X,  FN_X,   M_N,M_X,      MT_X, N,MUL_X,     N,DIV_X,    WEN_Y,WA_RD,WB_PCR,REN_Y,WEN_N,I_X ,SYNC_N,N,N,Y),
-      MTPCR->    List(Y,     BR_N,  REN_N,REN_Y,A2_X,    A1_X,  DW_X,  FN_X,   M_N,M_X,      MT_X, N,MUL_X,     N,DIV_X,    WEN_N,WA_X, WB_X,  REN_N,WEN_Y,I_X ,SYNC_N,N,N,Y)
+      MTPCR->    List(Y,     BR_N,  REN_N,REN_Y,A2_X,    A1_X,  DW_X,  FN_X,   M_N,M_X,      MT_X, N,MUL_X,     N,DIV_X,    WEN_N,WA_X, WB_X,  REN_N,WEN_Y,I_X ,SYNC_N,N,N,Y),
+      RDTIME->   List(Y,     BR_N,  REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X,      MT_X, N,MUL_X,     N,DIV_X,    WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N)
       
       // Instructions that have not yet been implemented
 /*  
diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala
index d683ac14..ab0f6f02 100644
--- a/rocket/src/main/scala/dcache.scala
+++ b/rocket/src/main/scala/dcache.scala
@@ -303,9 +303,12 @@ class rocketDCacheDM(lines: Int) extends Component {
     p_store_valid <== Bool(false);
     db_array <== db_array.bitSet(p_store_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
   }
-  when (resolve_store || (state === s_write_amo)) {
+  when (resolve_store) {
     db_array <== db_array.bitSet(p_store_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
   }
+  when (state === s_write_amo) {
+    db_array <== db_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
+  }
   when (tag_we) {
     db_array <== db_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(0,1));
   }
@@ -357,7 +360,7 @@ class rocketDCacheDM(lines: Int) extends Component {
   amo_alu.io.wmask := amo_wmask;
   amo_alu.io.lhs := Mux(r_cpu_resp_val, resp_data, r_resp_data).toUFix;
   amo_alu.io.rhs := r_amo_data.toUFix;
-  val amo_alu_out = amo_alu.io.result;
+  val amo_alu_out = Cat(amo_alu.io.result,amo_alu.io.result);
   
   data_array.io.a := 
     Mux(drain_store || resolve_store, p_store_idx(PGIDX_BITS-1, offsetmsb-1),
@@ -515,4 +518,4 @@ class rocketDCacheAmoALU extends Component {
   io.result := alu_out;
 }
   
-}
\ No newline at end of file
+}
diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index 63ab7698..32bc74cd 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -370,13 +370,18 @@ class rocketDpath extends Component
     (~(ex_reg_rs1(63) ^ ex_reg_rs2(63)) & io.ctrl.br_ltu |
     ex_reg_rs1(63) & ~ex_reg_rs2(63)).toBool;
 
+  // time stamp counter
+  val tsc_reg = Reg(resetVal = UFix(0,64));
+  tsc_reg <== tsc_reg + UFix(1);
+  
 	// writeback select mux
   ex_wdata :=
     Mux(ex_reg_ctrl_ll_wb || ex_reg_ctrl_wen_pcr, ex_reg_rs1,
     Mux(ex_reg_ctrl_sel_wb === WB_PC,  Cat(Fill(64-VADDR_BITS, ex_reg_pc_plus4(VADDR_BITS-1)), ex_reg_pc_plus4),
     Mux(ex_reg_ctrl_sel_wb === WB_ALU, ex_alu_out,
     Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
-        Bits(0, 64))))).toBits;
+    Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg,
+        Bits(0, 64)))))).toBits;
         
   // memory stage
   mem_reg_pc                <== ex_reg_pc;