riscv/rocket-chip
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fixed dcache amo bug, cleaned up testharness, added RDTIME instruction

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This commit is contained in:
Rimas Avizienis 2011-11-16 02:04:28 -08:00
parent 886857fa47
commit 80b4253318
4 changed files with 15 additions and 7 deletions
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3
rocket/src/main/scala/consts.scala
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@ -79,8 +79,7 @@ object Constants
val WB_PC = UFix(0, 3);
val WB_ALU = UFix(1, 3);
val WB_PCR = UFix(2, 3);
val WB_CR = UFix(3, 3);
val WB_MUL = UFix(4, 3);
val WB_TSC = UFix(3, 3);
val N = UFix(0, 1);
val Y = UFix(1, 1);

3
rocket/src/main/scala/ctrl.scala
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@ -252,7 +252,8 @@ class rocketCtrl extends Component
FENCE_I-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_I,N,N,N),
CFLUSH-> List(Y, BR_N, REN_Y,REN_N,A2_X, A1_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,Y),
MFPCR-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PCR,REN_Y,WEN_N,I_X ,SYNC_N,N,N,Y),
MTPCR-> List(Y, BR_N, REN_N,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_Y,I_X ,SYNC_N,N,N,Y)
MTPCR-> List(Y, BR_N, REN_N,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_Y,I_X ,SYNC_N,N,N,Y),
RDTIME-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N)
// Instructions that have not yet been implemented
/*

7
rocket/src/main/scala/dcache.scala
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@ -303,9 +303,12 @@ class rocketDCacheDM(lines: Int) extends Component {
p_store_valid <== Bool(false);
db_array <== db_array.bitSet(p_store_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
}
when (resolve_store || (state === s_write_amo)) {
when (resolve_store) {
db_array <== db_array.bitSet(p_store_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
}
when (state === s_write_amo) {
db_array <== db_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
}
when (tag_we) {
db_array <== db_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(0,1));
}
@ -357,7 +360,7 @@ class rocketDCacheDM(lines: Int) extends Component {
amo_alu.io.wmask := amo_wmask;
amo_alu.io.lhs := Mux(r_cpu_resp_val, resp_data, r_resp_data).toUFix;
amo_alu.io.rhs := r_amo_data.toUFix;
val amo_alu_out = amo_alu.io.result;
val amo_alu_out = Cat(amo_alu.io.result,amo_alu.io.result);
data_array.io.a :=
Mux(drain_store || resolve_store, p_store_idx(PGIDX_BITS-1, offsetmsb-1),

7
rocket/src/main/scala/dpath.scala
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@ -370,13 +370,18 @@ class rocketDpath extends Component
(~(ex_reg_rs1(63) ^ ex_reg_rs2(63)) & io.ctrl.br_ltu |
ex_reg_rs1(63) & ~ex_reg_rs2(63)).toBool;
// time stamp counter
val tsc_reg = Reg(resetVal = UFix(0,64));
tsc_reg <== tsc_reg + UFix(1);
// writeback select mux
ex_wdata :=
Mux(ex_reg_ctrl_ll_wb || ex_reg_ctrl_wen_pcr, ex_reg_rs1,
Mux(ex_reg_ctrl_sel_wb === WB_PC, Cat(Fill(64-VADDR_BITS, ex_reg_pc_plus4(VADDR_BITS-1)), ex_reg_pc_plus4),
Mux(ex_reg_ctrl_sel_wb === WB_ALU, ex_alu_out,
Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
Bits(0, 64))))).toBits;
Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg,
Bits(0, 64)))))).toBits;
// memory stage
mem_reg_pc <== ex_reg_pc;