riscv/rocket-chip
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Remove redundant check in interrupt priority encoding

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chooseInterrupts already sorts M interrupts above S interrupts.
This commit is contained in:
Andrew Waterman 2017-08-17 22:23:42 -07:00
parent cbe7c51b50
commit 8087a205cc
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/CSR.scala
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@ -300,7 +300,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
val pending_interrupts = read_mip & reg_mie
val d_interrupts = reg_debugint << CSR.debugIntCause
val m_interrupts = Mux(reg_mstatus.prv <= PRV.S || (reg_mstatus.prv === PRV.M && reg_mstatus.mie), pending_interrupts & ~reg_mideleg, UInt(0))
val s_interrupts = Mux(m_interrupts === 0 && (reg_mstatus.prv < PRV.S || (reg_mstatus.prv === PRV.S && reg_mstatus.sie)), pending_interrupts & reg_mideleg, UInt(0))
val s_interrupts = Mux(reg_mstatus.prv < PRV.S || (reg_mstatus.prv === PRV.S && reg_mstatus.sie), pending_interrupts & reg_mideleg, UInt(0))
val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(s_interrupts, m_interrupts, d_interrupts))
val interruptMSB = BigInt(1) << (xLen-1)
val interruptCause = UInt(interruptMSB) + whichInterrupt