From 8087a205ccd7994cc2d9e4c562cc5417ea520f3b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 17 Aug 2017 22:23:42 -0700 Subject: [PATCH] Remove redundant check in interrupt priority encoding chooseInterrupts already sorts M interrupts above S interrupts. --- src/main/scala/rocket/CSR.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 202c8344..929ce31a 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -300,7 +300,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param val pending_interrupts = read_mip & reg_mie val d_interrupts = reg_debugint << CSR.debugIntCause val m_interrupts = Mux(reg_mstatus.prv <= PRV.S || (reg_mstatus.prv === PRV.M && reg_mstatus.mie), pending_interrupts & ~reg_mideleg, UInt(0)) - val s_interrupts = Mux(m_interrupts === 0 && (reg_mstatus.prv < PRV.S || (reg_mstatus.prv === PRV.S && reg_mstatus.sie)), pending_interrupts & reg_mideleg, UInt(0)) + val s_interrupts = Mux(reg_mstatus.prv < PRV.S || (reg_mstatus.prv === PRV.S && reg_mstatus.sie), pending_interrupts & reg_mideleg, UInt(0)) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(s_interrupts, m_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = UInt(interruptMSB) + whichInterrupt