riscv/rocket-chip
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nTiles -> nClients in LogicalNetworkConfig

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This commit is contained in:
Henry Cook 2013-02-28 21:05:04 -08:00
parent ce4c1aa566
commit 806f897fc4
2 changed files with 24 additions and 24 deletions
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30
src/main/scala/RocketChip.scala
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@ -22,7 +22,7 @@ class TileToCrossbarShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetwork
val in = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}.flip
val out = (new FIFOIO){(new BasicCrossbarIO){ data }}
}
io.out.bits.header.src := io.in.bits.header.src + UFix(lconf.nHubs)
io.out.bits.header.src := io.in.bits.header.src + UFix(lconf.nMasters)
io.out.bits.header.dst := io.in.bits.header.dst
io.out.bits.payload := io.in.bits.payload
io.out.valid := io.in.valid
@ -42,7 +42,7 @@ class HubToCrossbarShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkC
val out = (new FIFOIO){(new BasicCrossbarIO){ data }}
}
io.out.bits.header.src := io.in.bits.header.src
io.out.bits.header.dst := io.in.bits.header.dst + UFix(lconf.nHubs)
io.out.bits.header.dst := io.in.bits.header.dst + UFix(lconf.nMasters)
io.out.bits.payload := io.in.bits.payload
io.out.valid := io.in.valid
io.in.ready := io.out.ready
@ -61,7 +61,7 @@ class CrossbarToTileShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetwork
val out = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}
}
io.out.bits.header.src := io.in.bits.header.src
io.out.bits.header.dst := io.in.bits.header.dst - UFix(lconf.nHubs)
io.out.bits.header.dst := io.in.bits.header.dst - UFix(lconf.nMasters)
io.out.bits.payload := io.in.bits.payload
io.out.valid := io.in.valid
io.in.ready := io.out.ready
@ -79,7 +79,7 @@ class CrossbarToHubShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkC
val in = (new FIFOIO){(new BasicCrossbarIO){ data }}.flip
val out = (new MasterSourcedIO){(new LogicalNetworkIO){ data }}.flip
}
io.out.bits.header.src := io.in.bits.header.src - UFix(lconf.nHubs)
io.out.bits.header.src := io.in.bits.header.src - UFix(lconf.nMasters)
io.out.bits.header.dst := io.in.bits.header.dst
io.out.bits.payload := io.in.bits.payload
io.out.valid := io.in.valid
@ -201,9 +201,9 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
{
implicit val lnconf = conf.ln
val io = new Bundle {
val tiles = Vec(conf.ln.nTiles) { new TileLinkIO }.flip
val tiles = Vec(conf.ln.nClients) { new TileLinkIO }.flip
val htif = (new TileLinkIO).flip
val incoherent = Vec(conf.ln.nTiles) { Bool() }.asInput
val incoherent = Vec(conf.ln.nClients) { Bool() }.asInput
val mem_backup = new ioMemSerialized(htif_width)
val mem_backup_en = Bool(INPUT)
val mem = new ioMemPipe
@ -213,9 +213,9 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
val lnWithHtifConf = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1,
idBits = log2Up(conf.ln.nEndpoints+1)+1,
nTiles = conf.ln.nTiles+1)
nClients = conf.ln.nClients+1)
val chWithHtifConf = conf.copy(ln = lnWithHtifConf)
require(tileEndpoints.length == lnWithHtifConf.nTiles)
require(tileEndpoints.length == lnWithHtifConf.nClients)
//val hub = new CoherenceHubBroadcast()(chWithHtifConf)
val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) }
val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
@ -231,14 +231,14 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
//hub.io.tiles <> adapter.io.hub
hub.io.network <> net.io(0)
for (i <- 1 to conf.ln.nTiles) {
for (i <- 1 to conf.ln.nClients) {
net.io(i) <> io.tiles(i-1)
//hub.io.tiles(i-1) <> io.tiles(i-1)
hub.io.incoherent(i-1) := io.incoherent(i-1)
}
net.io(conf.ln.nTiles+1) <> io.htif
//hub.io.tiles(conf.ln.nTiles) <> io.htif
hub.io.incoherent(conf.ln.nTiles) := Bool(true)
net.io(conf.ln.nClients+1) <> io.htif
//hub.io.tiles(conf.ln.nClients) <> io.htif
hub.io.incoherent(conf.ln.nClients) := Bool(true)
llc.io.cpu.req_cmd <> Queue(hub.io.mem.req_cmd)
llc.io.cpu.req_data <> Queue(hub.io.mem.req_data, REFILL_CYCLES)
@ -276,9 +276,9 @@ class Uncore(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent])(implicit
val mem_backup = new ioMemSerialized(htif_width)
val mem_backup_en = Bool(INPUT)
val mem = new ioMemPipe
val tiles = Vec(conf.ln.nTiles) { new TileLinkIO }.flip
val htif = Vec(conf.ln.nTiles) { new HTIFIO(conf.ln.nTiles) }.flip
val incoherent = Vec(conf.ln.nTiles) { Bool() }.asInput
val tiles = Vec(conf.ln.nClients) { new TileLinkIO }.flip
val htif = Vec(conf.ln.nClients) { new HTIFIO(conf.ln.nClients) }.flip
val incoherent = Vec(conf.ln.nClients) { Bool() }.asInput
}
val htif = new rocketHTIF(htif_width)

18
src/main/scala/fpga.scala
View File

@ -11,20 +11,20 @@ class FPGAUncore(htif_width: Int)(implicit conf: CoherenceHubConfiguration) exte
val io = new Bundle {
val host = new HostIO(htif_width)
val mem = new ioMem
val tiles = Vec(conf.ln.nTiles) { new TileLinkIO()(conf.ln) }.flip
val htif = Vec(conf.ln.nTiles) { new HTIFIO(conf.ln.nTiles) }.flip
val incoherent = Vec(conf.ln.nTiles) { Bool() }.asInput
val tiles = Vec(conf.ln.nClients) { new TileLinkIO()(conf.ln) }.flip
val htif = Vec(conf.ln.nClients) { new HTIFIO(conf.ln.nClients) }.flip
val incoherent = Vec(conf.ln.nClients) { Bool() }.asInput
}
val htif = new rocketHTIF(htif_width)
htif.io.cpu <> io.htif
io.host <> htif.io.host
val lnWithHtif = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1, nTiles = conf.ln.nTiles+1)
val lnWithHtif = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1, nClients = conf.ln.nClients+1)
val hub = new CoherenceHubBroadcast()(conf.copy(ln = lnWithHtif))
for (i <- 0 until conf.ln.nTiles)
for (i <- 0 until conf.ln.nClients)
hub.io.tiles(i) <> io.tiles(i)
hub.io.tiles(conf.ln.nTiles) <> htif.io.mem
hub.io.tiles(conf.ln.nClients) <> htif.io.mem
hub.io.incoherent <> io.incoherent
io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
@ -44,17 +44,17 @@ class FPGATop extends Component {
implicit val uconf = CoherenceHubConfiguration(co, lnConf)
val uncore = new FPGAUncore(htif_width = htif_width)
val resetSigs = Vec(uconf.ln.nTiles){ Bool() }
val resetSigs = Vec(uconf.ln.nClients){ Bool() }
val ic = ICacheConfig(64, 1, co, ntlb = 4, nbtb = 4)
val dc = DCacheConfig(64, 1, co, ntlb = 4,
nmshr = 2, nrpq = 16, nsdq = 17)
val rc = RocketConfiguration(uconf.ln, co, ic, dc,
fastMulDiv = false,
fpu = false, vec = false)
val tileList = (0 until uconf.ln.nTiles).map(r => new Tile(resetSignal = resetSigs(r))(rc))
val tileList = (0 until uconf.ln.nClients).map(r => new Tile(resetSignal = resetSigs(r))(rc))
io.debug.error_mode := Bool(false)
for (i <- 0 until uconf.ln.nTiles) {
for (i <- 0 until uconf.ln.nClients) {
val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i)
val il = uncore.io.incoherent(i)