riscv/rocket-chip
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This commit is contained in:
Andrew Waterman 2013-09-15 04:25:26 -07:00
parent fbdbb01232
commit 80003b3019
4 changed files with 4 additions and 5 deletions
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2
riscv-tests

@ -1 +1 @@
Subproject commit 728924ea6db6f6c3ee11554c3ad79d9bdabbe57e
Subproject commit 324c290f32f9c6e8953f14529d1e86659b2a2239

2
rocket

@ -1 +1 @@
Subproject commit 9b3b586bbbe38c7b455615a073716f6f6946df44
Subproject commit 688a0a7ed89ef0580993ac1352897a7d1814e47c

3
src/main/scala/RocketChip.scala
View File

@ -14,7 +14,6 @@ object DummyTopLevelConstants {
val HTIF_WIDTH = 16
val ENABLE_SHARING = true
val ENABLE_CLEAN_EXCLUSIVE = true
val HAS_VEC = false
val HAS_FPU = true
val NL2_REL_XACTS = 1
val NL2_ACQ_XACTS = 7
@ -249,7 +248,7 @@ class Top extends Module {
val dc = DCacheConfig(128, 4, ntlb = 8,
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
val rc = RocketConfiguration(tl, ic, dc,
fpu = HAS_FPU, vec = HAS_VEC)
fpu = HAS_FPU)
val io = new VLSITopIO(HTIF_WIDTH)

2
src/main/scala/fpga.scala
View File

@ -94,7 +94,7 @@ class FPGATop extends Module {
val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, states = co.nClientStates)
val rc = RocketConfiguration(tl, ic, dc,
fastMulDiv = false,
fpu = false, vec = false)
fpu = false)
val io = new FPGATopIO(htif_width)