diff --git a/riscv-tests b/riscv-tests
index 728924ea..324c290f 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit 728924ea6db6f6c3ee11554c3ad79d9bdabbe57e
+Subproject commit 324c290f32f9c6e8953f14529d1e86659b2a2239
diff --git a/rocket b/rocket
index 9b3b586b..688a0a7e 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 9b3b586bbbe38c7b455615a073716f6f6946df44
+Subproject commit 688a0a7ed89ef0580993ac1352897a7d1814e47c
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 4c304359..0abaf285 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -14,7 +14,6 @@ object DummyTopLevelConstants {
   val HTIF_WIDTH = 16
   val ENABLE_SHARING = true
   val ENABLE_CLEAN_EXCLUSIVE = true
-  val HAS_VEC = false
   val HAS_FPU = true
   val NL2_REL_XACTS = 1
   val NL2_ACQ_XACTS = 7
@@ -249,7 +248,7 @@ class Top extends Module {
   val dc = DCacheConfig(128, 4, ntlb = 8, 
                         nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
   val rc = RocketConfiguration(tl, ic, dc,
-                               fpu = HAS_FPU, vec = HAS_VEC)
+                               fpu = HAS_FPU)
 
   val io = new VLSITopIO(HTIF_WIDTH)
 
diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala
index 40034bf3..9c880e24 100644
--- a/src/main/scala/fpga.scala
+++ b/src/main/scala/fpga.scala
@@ -94,7 +94,7 @@ class FPGATop extends Module {
   val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, states = co.nClientStates)
   val rc = RocketConfiguration(tl, ic, dc,
                                fastMulDiv = false,
-                               fpu = false, vec = false)
+                               fpu = false)
 
   val io = new FPGATopIO(htif_width)