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refactor tilelink params

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This commit is contained in:
Henry Cook 2015-10-13 23:42:28 -07:00
parent 66ea39638e
commit 7fa3eb95e3
7 changed files with 213 additions and 176 deletions
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50
uncore/src/main/scala/broadcast.scala
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@ -31,17 +31,17 @@ class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
val internalDataBits = new DataQueueLocation().getWidth val internalDataBits = new DataQueueLocation().getWidth
val inStoreQueue :: inVolWBQueue :: inClientReleaseQueue :: Nil = Enum(UInt(), nDataQueueLocations) val inStoreQueue :: inVolWBQueue :: inClientReleaseQueue :: Nil = Enum(UInt(), nDataQueueLocations)
val trackerTLParams = p.alterPartial({ val usingStoreDataQueue = p.alterPartial({
case TLDataBits => internalDataBits case TLKey(`innerTLId`) => innerTLParams.copy()(internalDataBits, innerWriteMaskBits)
case TLWriteMaskBits => innerWriteMaskBits case TLKey(`outerTLId`) => outerTLParams.copy()(internalDataBits, outerWriteMaskBits)
}) })
// Create SHRs for outstanding transactions // Create SHRs for outstanding transactions
val trackerList = val trackerList =
(0 until nReleaseTransactors).map(id => (0 until nReleaseTransactors).map(id =>
Module(new BroadcastVoluntaryReleaseTracker(id))(trackerTLParams)) ++ Module(new BroadcastVoluntaryReleaseTracker(id)(usingStoreDataQueue))) ++
(nReleaseTransactors until nTransactors).map(id => (nReleaseTransactors until nTransactors).map(id =>
Module(new BroadcastAcquireTracker(id))(trackerTLParams)) Module(new BroadcastAcquireTracker(id)(usingStoreDataQueue)))
// Propagate incoherence flags // Propagate incoherence flags
trackerList.map(_.io.incoherent := io.incoherent) trackerList.map(_.io.incoherent := io.incoherent)
@ -105,10 +105,8 @@ class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
doInputRouting(io.inner.finish, trackerList.map(_.io.inner.finish)) doInputRouting(io.inner.finish, trackerList.map(_.io.inner.finish))
// Create an arbiter for the one memory port // Create an arbiter for the one memory port
val outer_arb = Module(new ClientUncachedTileLinkIOArbiter(trackerList.size)(p.alterPartial( val outer_arb = Module(new ClientUncachedTileLinkIOArbiter(trackerList.size)
{ case TLId => p(OuterTLId) (usingStoreDataQueue.alterPartial({ case TLId => p(OuterTLId) })))
case TLDataBits => internalDataBits
case TLWriteMaskBits => innerWriteMaskBits })))
outer_arb.io.in <> trackerList.map(_.io.outer) outer_arb.io.in <> trackerList.map(_.io.outer)
// Get the pending data out of the store data queue // Get the pending data out of the store data queue
val outer_data_ptr = new DataQueueLocation().fromBits(outer_arb.io.out.acquire.bits.data) val outer_data_ptr = new DataQueueLocation().fromBits(outer_arb.io.out.acquire.bits.data)
@ -137,8 +135,7 @@ class BroadcastVoluntaryReleaseTracker(trackerId: Int)
val s_idle :: s_outer :: s_grant :: s_ack :: Nil = Enum(UInt(), 4) val s_idle :: s_outer :: s_grant :: s_ack :: Nil = Enum(UInt(), 4)
val state = Reg(init=s_idle) val state = Reg(init=s_idle)
val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => p(InnerTLId); case TLDataBits => 0 })) val xact = Reg(new BufferedReleaseFromSrc()(p.alterPartial({ case TLId => innerTLId })))
val data_buffer = Reg(Vec(io.irel().data, innerDataBeats))
val coh = ManagerMetadata.onReset val coh = ManagerMetadata.onReset
val collect_irel_data = Reg(init=Bool(false)) val collect_irel_data = Reg(init=Bool(false))
@ -161,17 +158,17 @@ class BroadcastVoluntaryReleaseTracker(trackerId: Int)
io.inner.grant.bits := coh.makeGrant(xact, UInt(trackerId)) io.inner.grant.bits := coh.makeGrant(xact, UInt(trackerId))
//TODO: Use io.outer.release instead? //TODO: Use io.outer.release instead?
io.outer.acquire.bits := Bundle( io.outer.acquire.bits := PutBlock(
PutBlock( client_xact_id = UInt(trackerId),
client_xact_id = UInt(trackerId), addr_block = xact.addr_block,
addr_block = xact.addr_block, addr_beat = oacq_data_cnt,
addr_beat = oacq_data_cnt, data = xact.data_buffer(oacq_data_cnt))
data = data_buffer(oacq_data_cnt)))(outerTLParams) (p.alterPartial({ case TLId => outerTLId }))
when(collect_irel_data) { when(collect_irel_data) {
io.inner.release.ready := Bool(true) io.inner.release.ready := Bool(true)
when(io.inner.release.valid) { when(io.inner.release.valid) {
data_buffer(io.irel().addr_beat) := io.irel().data xact.data_buffer(io.irel().addr_beat) := io.irel().data
irel_data_valid := irel_data_valid.bitSet(io.irel().addr_beat, Bool(true)) irel_data_valid := irel_data_valid.bitSet(io.irel().addr_beat, Bool(true))
} }
when(irel_data_done) { collect_irel_data := Bool(false) } when(irel_data_done) { collect_irel_data := Bool(false) }
@ -182,7 +179,7 @@ class BroadcastVoluntaryReleaseTracker(trackerId: Int)
io.inner.release.ready := Bool(true) io.inner.release.ready := Bool(true)
when( io.inner.release.valid ) { when( io.inner.release.valid ) {
xact := io.irel() xact := io.irel()
data_buffer(UInt(0)) := io.irel().data xact.data_buffer(UInt(0)) := io.irel().data
collect_irel_data := io.irel().hasMultibeatData() collect_irel_data := io.irel().hasMultibeatData()
irel_data_valid := io.irel().hasData() << io.irel().addr_beat irel_data_valid := io.irel().hasData() << io.irel().addr_beat
state := Mux(io.irel().hasData(), s_outer, state := Mux(io.irel().hasData(), s_outer,
@ -217,12 +214,7 @@ class BroadcastAcquireTracker(trackerId: Int)
val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_mem_resp :: s_ack :: Nil = Enum(UInt(), 7) val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_mem_resp :: s_ack :: Nil = Enum(UInt(), 7)
val state = Reg(init=s_idle) val state = Reg(init=s_idle)
val xact = Reg(Bundle(new AcquireFromSrc, { val xact = Reg(new BufferedAcquireFromSrc()(p.alterPartial({ case TLId => innerTLId })))
case TLId => p(InnerTLId)
case TLDataBits => 0
case TLWriteMaskBits => innerWriteMaskBits
}))
val data_buffer = Reg(Vec(io.iacq().data, innerDataBeats))
val coh = ManagerMetadata.onReset val coh = ManagerMetadata.onReset
assert(!(state != s_idle && xact.isBuiltInType() && assert(!(state != s_idle && xact.isBuiltInType() &&
@ -268,14 +260,14 @@ class BroadcastAcquireTracker(trackerId: Int)
client_xact_id = UInt(trackerId), client_xact_id = UInt(trackerId),
addr_block = xact.addr_block, addr_block = xact.addr_block,
addr_beat = xact.addr_beat, addr_beat = xact.addr_beat,
data = data_buffer(0), data = xact.data_buffer(0),
wmask = xact.wmask()) wmask = xact.wmask())
val oacq_write_block = PutBlock( val oacq_write_block = PutBlock(
client_xact_id = UInt(trackerId), client_xact_id = UInt(trackerId),
addr_block = xact.addr_block, addr_block = xact.addr_block,
addr_beat = oacq_data_cnt, addr_beat = oacq_data_cnt,
data = data_buffer(oacq_data_cnt)) data = xact.data_buffer(oacq_data_cnt))
val oacq_read_beat = Get( val oacq_read_beat = Get(
client_xact_id = UInt(trackerId), client_xact_id = UInt(trackerId),
@ -321,7 +313,7 @@ class BroadcastAcquireTracker(trackerId: Int)
when(collect_iacq_data) { when(collect_iacq_data) {
io.inner.acquire.ready := Bool(true) io.inner.acquire.ready := Bool(true)
when(io.inner.acquire.valid) { when(io.inner.acquire.valid) {
data_buffer(io.iacq().addr_beat) := io.iacq().data xact.data_buffer(io.iacq().addr_beat) := io.iacq().data
iacq_data_valid := iacq_data_valid.bitSet(io.iacq().addr_beat, Bool(true)) iacq_data_valid := iacq_data_valid.bitSet(io.iacq().addr_beat, Bool(true))
} }
when(iacq_data_done) { collect_iacq_data := Bool(false) } when(iacq_data_done) { collect_iacq_data := Bool(false) }
@ -338,7 +330,7 @@ class BroadcastAcquireTracker(trackerId: Int)
io.inner.acquire.ready := Bool(true) io.inner.acquire.ready := Bool(true)
when(io.inner.acquire.valid) { when(io.inner.acquire.valid) {
xact := io.iacq() xact := io.iacq()
data_buffer(UInt(0)) := io.iacq().data xact.data_buffer(UInt(0)) := io.iacq().data
collect_iacq_data := io.iacq().hasMultibeatData() collect_iacq_data := io.iacq().hasMultibeatData()
iacq_data_valid := io.iacq().hasData() << io.iacq().addr_beat iacq_data_valid := io.iacq().hasData() << io.iacq().addr_beat
val needs_probes = mask_incoherent.orR val needs_probes = mask_incoherent.orR

44
uncore/src/main/scala/cache.scala
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@ -173,7 +173,7 @@ case object L2DirectoryRepresentation extends Field[DirectoryRepresentation]
trait HasL2HellaCacheParameters extends HasCacheParameters with HasCoherenceAgentParameters { trait HasL2HellaCacheParameters extends HasCacheParameters with HasCoherenceAgentParameters {
val idxMSB = idxBits-1 val idxMSB = idxBits-1
val idxLSB = 0 val idxLSB = 0
val blockAddrBits = p(TLBlockAddrBits) //val blockAddrBits = p(TLBlockAddrBits)
val refillCyclesPerBeat = outerDataBits/rowBits val refillCyclesPerBeat = outerDataBits/rowBits
val refillCycles = refillCyclesPerBeat*outerDataBeats val refillCycles = refillCyclesPerBeat*outerDataBeats
val internalDataBeats = p(CacheBlockBytes)*8/rowBits val internalDataBeats = p(CacheBlockBytes)*8/rowBits
@ -419,7 +419,8 @@ class TSHRFile(implicit p: Parameters) extends L2HellaCacheModule()(p)
// Create an arbiter for the one memory port // Create an arbiter for the one memory port
val outerList = trackerList.map(_.io.outer) :+ wb.io.outer val outerList = trackerList.map(_.io.outer) :+ wb.io.outer
val outer_arb = Module(new ClientTileLinkIOArbiter(outerList.size))(outerTLParams) val outer_arb = Module(new ClientTileLinkIOArbiter(outerList.size)
(p.alterPartial({ case TLId => p(OuterTLId)})))
outer_arb.io.in <> outerList outer_arb.io.in <> outerList
io.outer <> outer_arb.io.out io.outer <> outer_arb.io.out
@ -508,8 +509,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters) extends
val s_idle :: s_meta_read :: s_meta_resp :: s_busy :: s_meta_write :: Nil = Enum(UInt(), 5) val s_idle :: s_meta_read :: s_meta_resp :: s_busy :: s_meta_write :: Nil = Enum(UInt(), 5)
val state = Reg(init=s_idle) val state = Reg(init=s_idle)
val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => p(InnerTLId); case TLDataBits => 0 })) val xact = Reg(Bundle(new BufferedReleaseFromSrc()(p.alterPartial({case TLId => p(InnerTLId)}))))
val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits)))
val xact_way_en = Reg{ Bits(width = nWays) } val xact_way_en = Reg{ Bits(width = nWays) }
val xact_old_meta = Reg{ new L2Metadata } val xact_old_meta = Reg{ new L2Metadata }
val coh = xact_old_meta.coh val coh = xact_old_meta.coh
@ -525,7 +525,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters) extends
// Accept a voluntary Release (and any further beats of data) // Accept a voluntary Release (and any further beats of data)
pending_irels := (pending_irels & dropPendingBitWhenBeatHasData(io.inner.release)) pending_irels := (pending_irels & dropPendingBitWhenBeatHasData(io.inner.release))
io.inner.release.ready := state === s_idle || pending_irels.orR io.inner.release.ready := state === s_idle || pending_irels.orR
when(io.inner.release.fire()) { data_buffer(io.irel().addr_beat) := io.irel().data } when(io.inner.release.fire()) { xact.data_buffer(io.irel().addr_beat) := io.irel().data }
// Begin a transaction by getting the current block metadata // Begin a transaction by getting the current block metadata
io.meta.read.valid := state === s_meta_read io.meta.read.valid := state === s_meta_read
@ -543,7 +543,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters) extends
io.data.write.bits.addr_idx := xact.addr_block(idxMSB,idxLSB) io.data.write.bits.addr_idx := xact.addr_block(idxMSB,idxLSB)
io.data.write.bits.addr_beat := curr_write_beat io.data.write.bits.addr_beat := curr_write_beat
io.data.write.bits.wmask := ~UInt(0, io.data.write.bits.wmask.getWidth) io.data.write.bits.wmask := ~UInt(0, io.data.write.bits.wmask.getWidth)
io.data.write.bits.data := data_buffer(curr_write_beat) io.data.write.bits.data := xact.data_buffer(curr_write_beat)
// Send an acknowledgement // Send an acknowledgement
io.inner.grant.valid := state === s_busy && pending_ignt && !pending_irels io.inner.grant.valid := state === s_busy && pending_ignt && !pending_irels
@ -603,8 +603,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
val state = Reg(init=s_idle) val state = Reg(init=s_idle)
// State holding transaction metadata // State holding transaction metadata
val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => p(InnerTLId) })) val xact = Reg(Bundle(new BufferedAcquireFromSrc()(p.alterPartial({ case TLId => p(InnerTLId) }))))
val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits)))
val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits/8))) val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits/8)))
val xact_tag_match = Reg{ Bool() } val xact_tag_match = Reg{ Bool() }
val xact_way_en = Reg{ Bits(width = nWays) } val xact_way_en = Reg{ Bits(width = nWays) }
@ -612,7 +611,8 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
val pending_coh = Reg{ xact_old_meta.coh } val pending_coh = Reg{ xact_old_meta.coh }
// Secondary miss queue // Secondary miss queue
val ignt_q = Module(new Queue(new SecondaryMissInfo, nSecondaryMisses))(innerTLParams) val ignt_q = Module(new Queue(new SecondaryMissInfo()(p.alterPartial({ case TLId => p(InnerTLId) })),
nSecondaryMisses))
// State holding progress made on processing this transaction // State holding progress made on processing this transaction
val iacq_data_done = connectIncomingDataBeatCounter(io.inner.acquire) val iacq_data_done = connectIncomingDataBeatCounter(io.inner.acquire)
@ -657,8 +657,8 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
amoalu.io.cmd := xact.op_code() amoalu.io.cmd := xact.op_code()
amoalu.io.typ := xact.op_size() amoalu.io.typ := xact.op_size()
amoalu.io.lhs := io.data.resp.bits.data // default, overwritten by calls to mergeData amoalu.io.lhs := io.data.resp.bits.data // default, overwritten by calls to mergeData
amoalu.io.rhs := data_buffer.head // default, overwritten by calls to mergeData amoalu.io.rhs := xact.data_buffer.head // default, overwritten by calls to mergeData
val amo_result = xact.data // Reuse xact buffer space to store AMO result val amo_result = Reg(init = UInt(0, xact.tlDataBits))
// Utility functions for updating the data and metadata that will be kept in // Utility functions for updating the data and metadata that will be kept in
// the cache or granted to the original requestor after this transaction: // the cache or granted to the original requestor after this transaction:
@ -672,11 +672,11 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
def mergeData(dataBits: Int)(beat: UInt, incoming: UInt) { def mergeData(dataBits: Int)(beat: UInt, incoming: UInt) {
val old_data = incoming // Refilled, written back, or de-cached data val old_data = incoming // Refilled, written back, or de-cached data
val new_data = data_buffer(beat) // Newly Put data is already in the buffer val new_data = xact.data_buffer(beat) // Newly Put data is already in the buffer
amoalu.io.lhs := old_data >> xact.amo_shift_bits() amoalu.io.lhs := old_data >> xact.amo_shift_bits()
amoalu.io.rhs := new_data >> xact.amo_shift_bits() amoalu.io.rhs := new_data >> xact.amo_shift_bits()
val wmask = FillInterleaved(8, wmask_buffer(beat)) val wmask = FillInterleaved(8, wmask_buffer(beat))
data_buffer(beat) := ~wmask & old_data | xact.data_buffer(beat) := ~wmask & old_data |
wmask & Mux(xact.isBuiltInType(Acquire.putAtomicType), wmask & Mux(xact.isBuiltInType(Acquire.putAtomicType),
amoalu.io.out << xact.amo_shift_bits(), amoalu.io.out << xact.amo_shift_bits(),
new_data) new_data)
@ -780,14 +780,12 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
// built-in Acquire from the inner TL to the outer TL // built-in Acquire from the inner TL to the outer TL
io.outer.acquire.valid := state === s_outer_acquire && io.outer.acquire.valid := state === s_outer_acquire &&
(xact.allocate() || !pending_puts(oacq_data_idx)) (xact.allocate() || !pending_puts(oacq_data_idx))
io.outer.acquire.bits := Mux( io.outer.acquire.bits := Mux(xact.allocate(), xact_old_meta.coh.outer, ClientMetadata.onReset)
xact.allocate(), .makeAcquire(
xact_old_meta.coh.outer.makeAcquire(
client_xact_id = UInt(0), client_xact_id = UInt(0),
addr_block = xact.addr_block, addr_block = xact.addr_block,
op_code = xact.op_code()), op_code = xact.op_code())
Bundle(Acquire(xact))(outerTLParams)) io.oacq().data := xact.data_buffer(oacq_data_idx)
io.oacq().data := data_buffer(oacq_data_idx)
// Handle the response from outer memory // Handle the response from outer memory
io.outer.grant.ready := state === s_busy io.outer.grant.ready := state === s_busy
@ -814,7 +812,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
manager_xact_id = UInt(trackerId), manager_xact_id = UInt(trackerId),
data = Mux(xact.is(Acquire.putAtomicType), data = Mux(xact.is(Acquire.putAtomicType),
amo_result, amo_result,
data_buffer(ignt_data_idx))) xact.data_buffer(ignt_data_idx)))
io.inner.grant.bits.addr_beat := ignt_data_idx // override based on outgoing counter io.inner.grant.bits.addr_beat := ignt_data_idx // override based on outgoing counter
val pending_coh_on_ignt = HierarchicalMetadata( val pending_coh_on_ignt = HierarchicalMetadata(
@ -864,7 +862,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
io.data.write.bits.addr_idx := xact.addr_block(idxMSB,idxLSB) io.data.write.bits.addr_idx := xact.addr_block(idxMSB,idxLSB)
io.data.write.bits.addr_beat := curr_write_beat io.data.write.bits.addr_beat := curr_write_beat
io.data.write.bits.wmask := wmask_buffer(curr_write_beat) io.data.write.bits.wmask := wmask_buffer(curr_write_beat)
io.data.write.bits.data := data_buffer(curr_write_beat) io.data.write.bits.data := xact.data_buffer(curr_write_beat)
// End a transaction by updating the block metadata // End a transaction by updating the block metadata
io.meta.write.valid := state === s_meta_write io.meta.write.valid := state === s_meta_write
@ -879,7 +877,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
val beat = io.iacq().addr_beat val beat = io.iacq().addr_beat
val wmask = io.iacq().wmask() val wmask = io.iacq().wmask()
val full = FillInterleaved(8, wmask) val full = FillInterleaved(8, wmask)
data_buffer(beat) := (~full & data_buffer(beat)) | (full & io.iacq().data) xact.data_buffer(beat) := (~full & xact.data_buffer(beat)) | (full & io.iacq().data)
wmask_buffer(beat) := wmask | Mux(state === s_idle, Bits(0), wmask_buffer(beat)) wmask_buffer(beat) := wmask | Mux(state === s_idle, Bits(0), wmask_buffer(beat))
} }
@ -892,7 +890,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
// State machine updates and transaction handler metadata intialization // State machine updates and transaction handler metadata intialization
when(state === s_idle && io.inner.acquire.valid) { when(state === s_idle && io.inner.acquire.valid) {
xact := io.iacq() xact := io.iacq()
xact.data := UInt(0) amo_result := UInt(0)
pending_puts := Mux( // Make sure to collect all data from a PutBlock pending_puts := Mux( // Make sure to collect all data from a PutBlock
io.iacq().isBuiltInType(Acquire.putBlockType), io.iacq().isBuiltInType(Acquire.putBlockType),
dropPendingBitWhenBeatHasData(io.inner.acquire), dropPendingBitWhenBeatHasData(io.inner.acquire),

50
uncore/src/main/scala/coherence.scala
View File

@ -90,18 +90,18 @@ trait HasManagerSideCoherencePolicy extends HasDirectoryRepresentation {
def masterStateWidth = log2Ceil(nManagerStates) def masterStateWidth = log2Ceil(nManagerStates)
// Transaction probing logic // Transaction probing logic
def requiresProbes(acq: Acquire, meta: ManagerMetadata): Bool def requiresProbes(acq: AcquireMetadata, meta: ManagerMetadata): Bool
def requiresProbes(cmd: UInt, meta: ManagerMetadata): Bool def requiresProbes(cmd: UInt, meta: ManagerMetadata): Bool
// Determine which custom message type to use in response // Determine which custom message type to use in response
def getProbeType(cmd: UInt, meta: ManagerMetadata): UInt def getProbeType(cmd: UInt, meta: ManagerMetadata): UInt
def getProbeType(acq: Acquire, meta: ManagerMetadata): UInt def getProbeType(acq: AcquireMetadata, meta: ManagerMetadata): UInt
def getGrantType(acq: Acquire, meta: ManagerMetadata): UInt def getGrantType(acq: AcquireMetadata, meta: ManagerMetadata): UInt
def getExclusiveGrantType(): UInt def getExclusiveGrantType(): UInt
// Mutate ManagerMetadata based on messages or cmds // Mutate ManagerMetadata based on messages or cmds
def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata): ManagerMetadata def managerMetadataOnRelease(incoming: ReleaseMetadata, src: UInt, meta: ManagerMetadata): ManagerMetadata
def managerMetadataOnGrant(outgoing: Grant, dst: UInt, meta: ManagerMetadata) = def managerMetadataOnGrant(outgoing: GrantMetadata, dst: UInt, meta: ManagerMetadata) =
ManagerMetadata(sharers=Mux(outgoing.isBuiltInType(), // Assumes all built-ins are uncached ManagerMetadata(sharers=Mux(outgoing.isBuiltInType(), // Assumes all built-ins are uncached
meta.sharers, meta.sharers,
dir.push(meta.sharers, dst)))(meta.p) dir.push(meta.sharers, dst)))(meta.p)
@ -171,7 +171,7 @@ class MICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
// Manager states and functions: // Manager states and functions:
val nManagerStates = 0 // We don't actually need any states for this protocol val nManagerStates = 0 // We don't actually need any states for this protocol
def requiresProbes(a: Acquire, meta: ManagerMetadata) = !dir.none(meta.sharers) def requiresProbes(a: AcquireMetadata, meta: ManagerMetadata) = !dir.none(meta.sharers)
def requiresProbes(cmd: UInt, meta: ManagerMetadata) = !dir.none(meta.sharers) def requiresProbes(cmd: UInt, meta: ManagerMetadata) = !dir.none(meta.sharers)
@ -179,7 +179,7 @@ class MICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
MuxLookup(cmd, probeCopy, Array( MuxLookup(cmd, probeCopy, Array(
M_FLUSH -> probeInvalidate)) M_FLUSH -> probeInvalidate))
def getProbeType(a: Acquire, meta: ManagerMetadata): UInt = def getProbeType(a: AcquireMetadata, meta: ManagerMetadata): UInt =
Mux(a.isBuiltInType(), Mux(a.isBuiltInType(),
MuxLookup(a.a_type, probeCopy, Array( MuxLookup(a.a_type, probeCopy, Array(
Acquire.getBlockType -> probeCopy, Acquire.getBlockType -> probeCopy,
@ -189,10 +189,10 @@ class MICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
Acquire.putAtomicType -> probeInvalidate)), Acquire.putAtomicType -> probeInvalidate)),
probeInvalidate) probeInvalidate)
def getGrantType(a: Acquire, meta: ManagerMetadata): UInt = grantExclusive def getGrantType(a: AcquireMetadata, meta: ManagerMetadata): UInt = grantExclusive
def getExclusiveGrantType(): UInt = grantExclusive def getExclusiveGrantType(): UInt = grantExclusive
def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = { def managerMetadataOnRelease(incoming: ReleaseMetadata, src: UInt, meta: ManagerMetadata) = {
val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p) val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
MuxBundle(meta, Array( MuxBundle(meta, Array(
incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateData) -> popped,
@ -270,7 +270,7 @@ class MEICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
// Manager states and functions: // Manager states and functions:
val nManagerStates = 0 // We don't actually need any states for this protocol val nManagerStates = 0 // We don't actually need any states for this protocol
def requiresProbes(a: Acquire, meta: ManagerMetadata) = !dir.none(meta.sharers) def requiresProbes(a: AcquireMetadata, meta: ManagerMetadata) = !dir.none(meta.sharers)
def requiresProbes(cmd: UInt, meta: ManagerMetadata) = !dir.none(meta.sharers) def requiresProbes(cmd: UInt, meta: ManagerMetadata) = !dir.none(meta.sharers)
def getProbeType(cmd: UInt, meta: ManagerMetadata): UInt = def getProbeType(cmd: UInt, meta: ManagerMetadata): UInt =
@ -278,7 +278,7 @@ class MEICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
M_FLUSH -> probeInvalidate, M_FLUSH -> probeInvalidate,
M_PRODUCE -> probeDowngrade)) M_PRODUCE -> probeDowngrade))
def getProbeType(a: Acquire, meta: ManagerMetadata): UInt = def getProbeType(a: AcquireMetadata, meta: ManagerMetadata): UInt =
Mux(a.isBuiltInType(), Mux(a.isBuiltInType(),
MuxLookup(a.a_type, probeCopy, Array( MuxLookup(a.a_type, probeCopy, Array(
Acquire.getBlockType -> probeCopy, Acquire.getBlockType -> probeCopy,
@ -288,10 +288,10 @@ class MEICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
Acquire.putAtomicType -> probeInvalidate)), Acquire.putAtomicType -> probeInvalidate)),
probeInvalidate) probeInvalidate)
def getGrantType(a: Acquire, meta: ManagerMetadata): UInt = grantExclusive def getGrantType(a: AcquireMetadata, meta: ManagerMetadata): UInt = grantExclusive
def getExclusiveGrantType(): UInt = grantExclusive def getExclusiveGrantType(): UInt = grantExclusive
def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = { def managerMetadataOnRelease(incoming: ReleaseMetadata, src: UInt, meta: ManagerMetadata) = {
val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p) val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
MuxBundle(meta, Array( MuxBundle(meta, Array(
incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateData) -> popped,
@ -376,7 +376,7 @@ class MSICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
// notification msg to track clean drops) // notification msg to track clean drops)
// Also could avoid probes on outer WBs. // Also could avoid probes on outer WBs.
def requiresProbes(a: Acquire, meta: ManagerMetadata) = def requiresProbes(a: AcquireMetadata, meta: ManagerMetadata) =
Mux(dir.none(meta.sharers), Bool(false), Mux(dir.none(meta.sharers), Bool(false),
Mux(dir.one(meta.sharers), Bool(true), //TODO: for now we assume it's Exclusive Mux(dir.one(meta.sharers), Bool(true), //TODO: for now we assume it's Exclusive
Mux(a.isBuiltInType(), a.hasData(), a.a_type != acquireShared))) Mux(a.isBuiltInType(), a.hasData(), a.a_type != acquireShared)))
@ -388,7 +388,7 @@ class MSICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
M_FLUSH -> probeInvalidate, M_FLUSH -> probeInvalidate,
M_PRODUCE -> probeDowngrade)) M_PRODUCE -> probeDowngrade))
def getProbeType(a: Acquire, meta: ManagerMetadata): UInt = def getProbeType(a: AcquireMetadata, meta: ManagerMetadata): UInt =
Mux(a.isBuiltInType(), Mux(a.isBuiltInType(),
MuxLookup(a.a_type, probeCopy, Array( MuxLookup(a.a_type, probeCopy, Array(
Acquire.getBlockType -> probeCopy, Acquire.getBlockType -> probeCopy,
@ -400,13 +400,13 @@ class MSICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
acquireShared -> probeDowngrade, acquireShared -> probeDowngrade,
acquireExclusive -> probeInvalidate))) acquireExclusive -> probeInvalidate)))
def getGrantType(a: Acquire, meta: ManagerMetadata): UInt = def getGrantType(a: AcquireMetadata, meta: ManagerMetadata): UInt =
Mux(a.a_type === acquireShared, Mux(a.a_type === acquireShared,
Mux(!dir.none(meta.sharers), grantShared, grantExclusive), Mux(!dir.none(meta.sharers), grantShared, grantExclusive),
grantExclusive) grantExclusive)
def getExclusiveGrantType(): UInt = grantExclusive def getExclusiveGrantType(): UInt = grantExclusive
def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = { def managerMetadataOnRelease(incoming: ReleaseMetadata, src: UInt, meta: ManagerMetadata) = {
val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p) val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
MuxBundle(meta, Array( MuxBundle(meta, Array(
incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateData) -> popped,
@ -493,7 +493,7 @@ class MESICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
// notification msg to track clean drops) // notification msg to track clean drops)
// Also could avoid probes on outer WBs. // Also could avoid probes on outer WBs.
def requiresProbes(a: Acquire, meta: ManagerMetadata) = def requiresProbes(a: AcquireMetadata, meta: ManagerMetadata) =
Mux(dir.none(meta.sharers), Bool(false), Mux(dir.none(meta.sharers), Bool(false),
Mux(dir.one(meta.sharers), Bool(true), //TODO: for now we assume it's Exclusive Mux(dir.one(meta.sharers), Bool(true), //TODO: for now we assume it's Exclusive
Mux(a.isBuiltInType(), a.hasData(), a.a_type != acquireShared))) Mux(a.isBuiltInType(), a.hasData(), a.a_type != acquireShared)))
@ -505,7 +505,7 @@ class MESICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
M_FLUSH -> probeInvalidate, M_FLUSH -> probeInvalidate,
M_PRODUCE -> probeDowngrade)) M_PRODUCE -> probeDowngrade))
def getProbeType(a: Acquire, meta: ManagerMetadata): UInt = def getProbeType(a: AcquireMetadata, meta: ManagerMetadata): UInt =
Mux(a.isBuiltInType(), Mux(a.isBuiltInType(),
MuxLookup(a.a_type, probeCopy, Array( MuxLookup(a.a_type, probeCopy, Array(
Acquire.getBlockType -> probeCopy, Acquire.getBlockType -> probeCopy,
@ -517,13 +517,13 @@ class MESICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
acquireShared -> probeDowngrade, acquireShared -> probeDowngrade,
acquireExclusive -> probeInvalidate))) acquireExclusive -> probeInvalidate)))
def getGrantType(a: Acquire, meta: ManagerMetadata): UInt = def getGrantType(a: AcquireMetadata, meta: ManagerMetadata): UInt =
Mux(a.a_type === acquireShared, Mux(a.a_type === acquireShared,
Mux(!dir.none(meta.sharers), grantShared, grantExclusive), Mux(!dir.none(meta.sharers), grantShared, grantExclusive),
grantExclusive) grantExclusive)
def getExclusiveGrantType(): UInt = grantExclusive def getExclusiveGrantType(): UInt = grantExclusive
def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = { def managerMetadataOnRelease(incoming: ReleaseMetadata, src: UInt, meta: ManagerMetadata) = {
val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p) val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
MuxBundle(meta, Array( MuxBundle(meta, Array(
incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateData) -> popped,
@ -631,7 +631,7 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d
// Manager states and functions: // Manager states and functions:
val nManagerStates = 0 // TODO: we could add some states to reduce the number of message types val nManagerStates = 0 // TODO: we could add some states to reduce the number of message types
def requiresProbes(a: Acquire, meta: ManagerMetadata) = def requiresProbes(a: AcquireMetadata, meta: ManagerMetadata) =
Mux(dir.none(meta.sharers), Bool(false), Mux(dir.none(meta.sharers), Bool(false),
Mux(dir.one(meta.sharers), Bool(true), //TODO: for now we assume it's Exclusive Mux(dir.one(meta.sharers), Bool(true), //TODO: for now we assume it's Exclusive
Mux(a.isBuiltInType(), a.hasData(), a.a_type != acquireShared))) Mux(a.isBuiltInType(), a.hasData(), a.a_type != acquireShared)))
@ -643,7 +643,7 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d
M_FLUSH -> probeInvalidate, M_FLUSH -> probeInvalidate,
M_PRODUCE -> probeDowngrade)) M_PRODUCE -> probeDowngrade))
def getProbeType(a: Acquire, meta: ManagerMetadata): UInt = def getProbeType(a: AcquireMetadata, meta: ManagerMetadata): UInt =
Mux(a.isBuiltInType(), Mux(a.isBuiltInType(),
MuxLookup(a.a_type, probeCopy, Array( MuxLookup(a.a_type, probeCopy, Array(
Acquire.getBlockType -> probeCopy, Acquire.getBlockType -> probeCopy,
@ -656,14 +656,14 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d
acquireExclusive -> probeInvalidate, acquireExclusive -> probeInvalidate,
acquireInvalidateOthers -> probeInvalidateOthers))) acquireInvalidateOthers -> probeInvalidateOthers)))
def getGrantType(a: Acquire, meta: ManagerMetadata): UInt = def getGrantType(a: AcquireMetadata, meta: ManagerMetadata): UInt =
MuxLookup(a.a_type, grantShared, Array( MuxLookup(a.a_type, grantShared, Array(
acquireShared -> Mux(!dir.none(meta.sharers), grantShared, grantExclusive), acquireShared -> Mux(!dir.none(meta.sharers), grantShared, grantExclusive),
acquireExclusive -> grantExclusive, acquireExclusive -> grantExclusive,
acquireInvalidateOthers -> grantExclusiveAck)) //TODO: add this to MESI for broadcast? acquireInvalidateOthers -> grantExclusiveAck)) //TODO: add this to MESI for broadcast?
def getExclusiveGrantType(): UInt = grantExclusive def getExclusiveGrantType(): UInt = grantExclusive
def managerMetadataOnRelease(incoming: Release, src: UInt, meta: ManagerMetadata) = { def managerMetadataOnRelease(incoming: ReleaseMetadata, src: UInt, meta: ManagerMetadata) = {
val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p) val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p)
MuxBundle(meta, Array( MuxBundle(meta, Array(
incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateData) -> popped,

24
uncore/src/main/scala/htif.scala
View File

@ -12,23 +12,23 @@ case class HtifParameters(width: Int, nCores: Int, offsetBits: Int, nSCR: Int =
trait HasHtifParameters { trait HasHtifParameters {
implicit val p: Parameters implicit val p: Parameters
lazy val external = p(HtifKey) val external = p(HtifKey)
lazy val dataBits = p(TLDataBits) val dataBits = p(TLKey(p(TLId))).dataBitsPerBeat
lazy val dataBeats = p(TLDataBeats) val dataBeats = p(TLKey(p(TLId))).dataBeats
lazy val w = external.width val w = external.width
lazy val nSCR = external.nSCR val nSCR = external.nSCR
lazy val scrAddrBits = log2Up(nSCR) val scrAddrBits = log2Up(nSCR)
lazy val scrDataBits = 64 val scrDataBits = 64
lazy val scrDataBytes = scrDataBits / 8 val scrDataBytes = scrDataBits / 8
lazy val offsetBits = external.offsetBits val offsetBits = external.offsetBits
lazy val nCores = external.nCores val nCores = external.nCores
} }
abstract class HtifModule(implicit val p: Parameters) extends Module with HasHtifParameters abstract class HtifModule(implicit val p: Parameters) extends Module with HasHtifParameters
abstract class HtifBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) abstract class HtifBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasHtifParameters with HasHtifParameters
class HostIO(implicit p: Parameters) extends HtifBundle()(p) { class HostIO(w: Int) extends Bundle {
val clk = Bool(OUTPUT) val clk = Bool(OUTPUT)
val clk_edge = Bool(OUTPUT) val clk_edge = Bool(OUTPUT)
val in = Decoupled(Bits(width = w)).flip val in = Decoupled(Bits(width = w)).flip
@ -49,7 +49,7 @@ class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHtifParameters { class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHtifParameters {
val io = new Bundle { val io = new Bundle {
val host = new HostIO val host = new HostIO(w)
val cpu = Vec(new HtifIO, nCores).flip val cpu = Vec(new HtifIO, nCores).flip
val mem = new ClientUncachedTileLinkIO val mem = new ClientUncachedTileLinkIO
val scr = new SMIIO(scrDataBits, scrAddrBits) val scr = new SMIIO(scrDataBits, scrAddrBits)

19
uncore/src/main/scala/metadata.scala
View File

@ -176,7 +176,7 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
def full(dummy: Int = 0): UInt = co.dir.full(this.sharers) def full(dummy: Int = 0): UInt = co.dir.full(this.sharers)
/** Does this [[uncore.Acquire]] require [[uncore.Probe Probes]] to be sent */ /** Does this [[uncore.Acquire]] require [[uncore.Probe Probes]] to be sent */
def requiresProbes(acq: Acquire): Bool = co.requiresProbes(acq, this) def requiresProbes(acq: AcquireMetadata): Bool = co.requiresProbes(acq, this)
/** Does this memory op require [[uncore.Probe Probes]] to be sent */ /** Does this memory op require [[uncore.Probe Probes]] to be sent */
def requiresProbes(op_code: UInt): Bool = co.requiresProbes(op_code, this) def requiresProbes(op_code: UInt): Bool = co.requiresProbes(op_code, this)
/** Does an eviction require [[uncore.Probe Probes]] to be sent */ /** Does an eviction require [[uncore.Probe Probes]] to be sent */
@ -188,7 +188,7 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
* @param dst Destination client id for this Probe * @param dst Destination client id for this Probe
* @param acq Acquire message triggering this Probe * @param acq Acquire message triggering this Probe
*/ */
def makeProbe(dst: UInt, acq: Acquire): ProbeToDst = def makeProbe(dst: UInt, acq: AcquireMetadata): ProbeToDst =
Bundle(Probe(dst, co.getProbeType(acq, this), acq.addr_block)(p)) Bundle(Probe(dst, co.getProbeType(acq, this), acq.addr_block)(p))
/** Construct an appropriate [[uncore.ProbeToDst]] for a given mem op /** Construct an appropriate [[uncore.ProbeToDst]] for a given mem op
@ -213,7 +213,7 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
* @param rel Release message being acknowledged by this Grant * @param rel Release message being acknowledged by this Grant
* @param manager_xact_id manager's transaction id * @param manager_xact_id manager's transaction id
*/ */
def makeGrant(rel: ReleaseFromSrc, manager_xact_id: UInt): GrantToDst = { def makeGrant(rel: ReleaseMetadata with HasClientId, manager_xact_id: UInt): GrantToDst = {
Bundle(Grant( Bundle(Grant(
dst = rel.client_id, dst = rel.client_id,
is_builtin_type = Bool(true), is_builtin_type = Bool(true),
@ -232,7 +232,7 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
* @param data data being refilled to the original requestor * @param data data being refilled to the original requestor
*/ */
def makeGrant( def makeGrant(
acq: AcquireFromSrc, acq: AcquireMetadata with HasClientId,
manager_xact_id: UInt, manager_xact_id: UInt,
addr_beat: UInt = UInt(0), addr_beat: UInt = UInt(0),
data: UInt = UInt(0)): GrantToDst = { data: UInt = UInt(0)): GrantToDst = {
@ -259,7 +259,7 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
* @param data data being refilled to the original requestor * @param data data being refilled to the original requestor
*/ */
def makeGrant( def makeGrant(
pri: AcquireFromSrc, pri: AcquireMetadata with HasClientId,
sec: SecondaryMissInfo, sec: SecondaryMissInfo,
manager_xact_id: UInt, manager_xact_id: UInt,
data: UInt): GrantToDst = { data: UInt): GrantToDst = {
@ -272,14 +272,14 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
* *
* @param incoming the incoming [[uncore.ReleaseFromSrc]] * @param incoming the incoming [[uncore.ReleaseFromSrc]]
*/ */
def onRelease(incoming: ReleaseFromSrc): ManagerMetadata = def onRelease(incoming: ReleaseMetadata with HasClientId): ManagerMetadata =
co.managerMetadataOnRelease(incoming, incoming.client_id, this) co.managerMetadataOnRelease(incoming, incoming.client_id, this)
/** New metadata after sending a [[uncore.GrantToDst]] /** New metadata after sending a [[uncore.GrantToDst]]
* *
* @param outgoing the outgoing [[uncore.GrantToDst]] * @param outgoing the outgoing [[uncore.GrantToDst]]
*/ */
def onGrant(outgoing: GrantToDst): ManagerMetadata = def onGrant(outgoing: GrantMetadata with HasClientId): ManagerMetadata =
co.managerMetadataOnGrant(outgoing, outgoing.client_id, this) co.managerMetadataOnGrant(outgoing, outgoing.client_id, this)
} }
@ -328,8 +328,3 @@ object HierarchicalMetadata {
def onReset(implicit p: Parameters): HierarchicalMetadata = def onReset(implicit p: Parameters): HierarchicalMetadata =
apply(ManagerMetadata.onReset, ClientMetadata.onReset) apply(ManagerMetadata.onReset, ClientMetadata.onReset)
} }
/** Identifies the TLId of the inner network in a hierarchical cache controller */
case object InnerTLId extends Field[String]
/** Identifies the TLId of the outer network in a hierarchical cache controller */
case object OuterTLId extends Field[String]

168
uncore/src/main/scala/tilelink.scala
View File

@ -5,58 +5,62 @@ import Chisel._
import junctions._ import junctions._
import scala.math.max import scala.math.max
case object TLId extends Field[String]
case class TLKey(id: String) extends Field[TileLinkParameters]
/** Parameters exposed to the top-level design, set based on /** Parameters exposed to the top-level design, set based on
* external requirements or design space exploration * external requirements or design space exploration
*/ *
/** Unique name per TileLink network*/ * Coherency policy used to define custom mesage types
case object TLId extends Field[String] * Number of manager agents
/** Coherency policy used to define custom mesage types */ * Number of client agents that cache data and use custom [[uncore.Acquire]] types
case object TLCoherencePolicy extends Field[CoherencePolicy] * Number of client agents that do not cache data and use built-in [[uncore.Acquire]] types
/** Number of manager agents */ * Maximum number of unique outstanding transactions per client
case object TLNManagers extends Field[Int] * Maximum number of clients multiplexed onto a single port
/** Number of client agents */ * Maximum number of unique outstanding transactions per manager
case object TLNClients extends Field[Int] * Width of cache block addresses
/** Number of client agents that cache data and use custom [[uncore.Acquire]] types */ * Total amount of data per cache block
case object TLNCachingClients extends Field[Int] * Number of data beats per cache block
/** Number of client agents that do not cache data and use built-in [[uncore.Acquire]] types */ **/
case object TLNCachelessClients extends Field[Int]
/** Maximum number of unique outstanding transactions per client */ case class TileLinkParameters(
case object TLMaxClientXacts extends Field[Int] coherencePolicy: CoherencePolicy,
/** Maximum number of clients multiplexed onto a single port */ nManagers: Int,
case object TLMaxClientsPerPort extends Field[Int] nCachingClients: Int,
/** Maximum number of unique outstanding transactions per manager */ nCachelessClients: Int,
case object TLMaxManagerXacts extends Field[Int] maxClientXacts: Int,
/** Width of cache block addresses */ maxClientsPerPort: Int,
case object TLBlockAddrBits extends Field[Int] maxManagerXacts: Int,
/** Width of data beats */ addrBits: Int,
case object TLDataBits extends Field[Int] dataBits: Int,
/** Number of data beats per cache block */ dataBeats: Int = 4)
case object TLDataBeats extends Field[Int] (val dataBitsPerBeat: Int = dataBits / dataBeats,
/** Whether the underlying physical network preserved point-to-point ordering of messages */ val writeMaskBits: Int = ((dataBits / dataBeats) - 1) / 8 + 1) {
case object TLNetworkIsOrderedP2P extends Field[Boolean] val nClients = nCachingClients + nCachelessClients
/** Number of bits in write mask (usually one per byte in beat) */ }
case object TLWriteMaskBits extends Field[Int]
/** Utility trait for building Modules and Bundles that use TileLink parameters */ /** Utility trait for building Modules and Bundles that use TileLink parameters */
trait HasTileLinkParameters { trait HasTileLinkParameters {
implicit val p: Parameters implicit val p: Parameters
val tlCoh = p(TLCoherencePolicy) val tlExternal = p(TLKey(p(TLId)))
val tlNManagers = p(TLNManagers) val tlCoh = tlExternal.coherencePolicy
val tlNClients = p(TLNClients) val tlNManagers = tlExternal.nManagers
val tlNCachingClients = p(TLNCachingClients) val tlNCachingClients = tlExternal.nCachingClients
val tlNCachelessClients = p(TLNCachelessClients) val tlNCachelessClients = tlExternal.nCachelessClients
val tlNClients = tlExternal.nClients
val tlClientIdBits = log2Up(tlNClients) val tlClientIdBits = log2Up(tlNClients)
val tlManagerIdBits = log2Up(tlNManagers) val tlManagerIdBits = log2Up(tlNManagers)
val tlMaxClientXacts = p(TLMaxClientXacts) val tlMaxClientXacts = tlExternal.maxClientXacts
val tlMaxClientsPerPort = p(TLMaxClientsPerPort) val tlMaxClientsPerPort = tlExternal.maxClientsPerPort
val tlMaxManagerXacts = p(TLMaxManagerXacts) val tlMaxManagerXacts = tlExternal.maxManagerXacts
val tlClientXactIdBits = log2Up(tlMaxClientXacts*tlMaxClientsPerPort) val tlClientXactIdBits = log2Up(tlMaxClientXacts*tlMaxClientsPerPort)
val tlManagerXactIdBits = log2Up(tlMaxManagerXacts) val tlManagerXactIdBits = log2Up(tlMaxManagerXacts)
val tlBlockAddrBits = p(TLBlockAddrBits) val tlBlockAddrBits = tlExternal.addrBits
val tlDataBits = p(TLDataBits) val tlDataBeats = tlExternal.dataBeats
val tlDataBits = tlExternal.dataBitsPerBeat
val tlDataBytes = tlDataBits/8 val tlDataBytes = tlDataBits/8
val tlDataBeats = p(TLDataBeats) val tlWriteMaskBits = tlExternal.writeMaskBits
val tlWriteMaskBits = p(TLWriteMaskBits)
val tlBeatAddrBits = log2Up(tlDataBeats) val tlBeatAddrBits = log2Up(tlDataBeats)
val tlByteAddrBits = log2Up(tlWriteMaskBits) val tlByteAddrBits = log2Up(tlWriteMaskBits)
val tlMemoryOpcodeBits = M_SZ val tlMemoryOpcodeBits = M_SZ
@ -69,7 +73,8 @@ trait HasTileLinkParameters {
tlMemoryOpcodeBits)) + 1 tlMemoryOpcodeBits)) + 1
val tlGrantTypeBits = max(log2Up(Grant.nBuiltInTypes), val tlGrantTypeBits = max(log2Up(Grant.nBuiltInTypes),
tlCoh.grantTypeWidth) + 1 tlCoh.grantTypeWidth) + 1
val tlNetworkPreservesPointToPointOrdering = p(TLNetworkIsOrderedP2P) /** Whether the underlying physical network preserved point-to-point ordering of messages */
val tlNetworkPreservesPointToPointOrdering = false
val tlNetworkDoesNotInterleaveBeats = true val tlNetworkDoesNotInterleaveBeats = true
val amoAluOperandBits = p(AmoAluOperandBits) val amoAluOperandBits = p(AmoAluOperandBits)
} }
@ -126,6 +131,11 @@ trait HasTileLinkData extends HasTileLinkBeatId {
def hasMultibeatData(dummy: Int = 0): Bool def hasMultibeatData(dummy: Int = 0): Bool
} }
/** An entire cache block of data */
trait HasTileLinkBlock extends HasTileLinkParameters {
val data_buffer = Vec(tlDataBeats, UInt(width = tlDataBits))
}
/** The id of a client source or destination. Used in managers. */ /** The id of a client source or destination. Used in managers. */
trait HasClientId extends HasTileLinkParameters { trait HasClientId extends HasTileLinkParameters {
val client_id = UInt(width = tlClientIdBits) val client_id = UInt(width = tlClientIdBits)
@ -141,10 +151,10 @@ trait HasClientId extends HasTileLinkParameters {
* PutAtomic built-in types. After sending an Acquire, clients must * PutAtomic built-in types. After sending an Acquire, clients must
* wait for a manager to send them a [[uncore.Grant]] message in response. * wait for a manager to send them a [[uncore.Grant]] message in response.
*/ */
class Acquire(implicit p: Parameters) extends ClientToManagerChannel()(p) class AcquireMetadata(implicit p: Parameters) extends ClientToManagerChannel()(p)
with HasCacheBlockAddress with HasCacheBlockAddress
with HasClientTransactionId with HasClientTransactionId
with HasTileLinkData { with HasTileLinkBeatId {
// Actual bundle fields: // Actual bundle fields:
val is_builtin_type = Bool() val is_builtin_type = Bool()
val a_type = UInt(width = tlAcquireTypeBits) val a_type = UInt(width = tlAcquireTypeBits)
@ -221,9 +231,18 @@ class Acquire(implicit p: Parameters) extends ClientToManagerChannel()(p)
} }
} }
/** [[uncore.AcquireMetadata]] with an extra field containing the data beat */
class Acquire(implicit p: Parameters) extends AcquireMetadata()(p) with HasTileLinkData
/** [[uncore.AcquireMetadata]] with an extra field containing the entire cache block */
class BufferedAcquire(implicit p: Parameters) extends AcquireMetadata()(p) with HasTileLinkBlock
/** [[uncore.Acquire]] with an extra field stating its source id */ /** [[uncore.Acquire]] with an extra field stating its source id */
class AcquireFromSrc(implicit p: Parameters) extends Acquire()(p) with HasClientId class AcquireFromSrc(implicit p: Parameters) extends Acquire()(p) with HasClientId
/** [[uncore.BufferedAcquire]] with an extra field stating its source id */
class BufferedAcquireFromSrc(implicit p: Parameters) extends BufferedAcquire()(p) with HasClientId
/** Contains definitions of the the built-in Acquire types and a factory /** Contains definitions of the the built-in Acquire types and a factory
* for [[uncore.Acquire]] * for [[uncore.Acquire]]
* *
@ -252,7 +271,7 @@ object Acquire {
def typesWithMultibeatData = Vec(putBlockType) def typesWithMultibeatData = Vec(putBlockType)
def typesOnSubBlocks = Vec(putType, getType, putAtomicType) def typesOnSubBlocks = Vec(putType, getType, putAtomicType)
def fullWriteMask(implicit p: Parameters) = SInt(-1, width = p(TLWriteMaskBits)).toUInt def fullWriteMask(implicit p: Parameters) = SInt(-1, width = p(TLKey(p(TLId))).writeMaskBits).toUInt
// Most generic constructor // Most generic constructor
def apply( def apply(
@ -550,10 +569,10 @@ object Probe {
* a particular [[uncore.CoherencePolicy]]. Releases may contain data or may be * a particular [[uncore.CoherencePolicy]]. Releases may contain data or may be
* simple acknowledgements. Voluntary Releases are acknowledged with [[uncore.Grant Grants]]. * simple acknowledgements. Voluntary Releases are acknowledged with [[uncore.Grant Grants]].
*/ */
class Release(implicit p: Parameters) extends ClientToManagerChannel()(p) class ReleaseMetadata(implicit p: Parameters) extends ClientToManagerChannel()(p)
with HasTileLinkBeatId
with HasCacheBlockAddress with HasCacheBlockAddress
with HasClientTransactionId with HasClientTransactionId {
with HasTileLinkData {
val r_type = UInt(width = tlCoh.releaseTypeWidth) val r_type = UInt(width = tlCoh.releaseTypeWidth)
val voluntary = Bool() val voluntary = Bool()
@ -567,9 +586,18 @@ class Release(implicit p: Parameters) extends ClientToManagerChannel()(p)
def full_addr(dummy: Int = 0) = Cat(this.addr_block, this.addr_beat, UInt(0, width = tlByteAddrBits)) def full_addr(dummy: Int = 0) = Cat(this.addr_block, this.addr_beat, UInt(0, width = tlByteAddrBits))
} }
/** [[uncore.ReleaseMetadata]] with an extra field containing the data beat */
class Release(implicit p: Parameters) extends ReleaseMetadata()(p) with HasTileLinkData
/** [[uncore.ReleaseMetadata]] with an extra field containing the entire cache block */
class BufferedRelease(implicit p: Parameters) extends ReleaseMetadata()(p) with HasTileLinkBlock
/** [[uncore.Release]] with an extra field stating its source id */ /** [[uncore.Release]] with an extra field stating its source id */
class ReleaseFromSrc(implicit p: Parameters) extends Release()(p) with HasClientId class ReleaseFromSrc(implicit p: Parameters) extends Release()(p) with HasClientId
/** [[uncore.BufferedRelease]] with an extra field stating its source id */
class BufferedReleaseFromSrc(implicit p: Parameters) extends BufferedRelease()(p) with HasClientId
/** Contains a [[uncore.Release]] factory /** Contains a [[uncore.Release]] factory
* *
* In general you should avoid using this factory directly and use * In general you should avoid using this factory directly and use
@ -609,8 +637,8 @@ object Release {
* coherence policies may also define custom Grant types. Grants may contain data * coherence policies may also define custom Grant types. Grants may contain data
* or may be simple acknowledgements. Grants are responded to with [[uncore.Finish]]. * or may be simple acknowledgements. Grants are responded to with [[uncore.Finish]].
*/ */
class Grant(implicit p: Parameters) extends ManagerToClientChannel()(p) class GrantMetadata(implicit p: Parameters) extends ManagerToClientChannel()(p)
with HasTileLinkData with HasTileLinkBeatId
with HasClientTransactionId with HasClientTransactionId
with HasManagerTransactionId { with HasManagerTransactionId {
val is_builtin_type = Bool() val is_builtin_type = Bool()
@ -636,9 +664,18 @@ class Grant(implicit p: Parameters) extends ManagerToClientChannel()(p)
} }
} }
/** [[uncore.GrantMetadata]] with an extra field containing a single beat of data */
class Grant(implicit p: Parameters) extends GrantMetadata()(p) with HasTileLinkData
/** [[uncore.Grant]] with an extra field stating its destination */ /** [[uncore.Grant]] with an extra field stating its destination */
class GrantToDst(implicit p: Parameters) extends Grant()(p) with HasClientId class GrantToDst(implicit p: Parameters) extends Grant()(p) with HasClientId
/** [[uncore.GrantMetadata]] with an extra field containing an entire cache block */
class BufferedGrant(implicit p: Parameters) extends GrantMetadata()(p) with HasTileLinkBlock
/** [[uncore.BufferedGrant]] with an extra field stating its destination */
class BufferedGrantToDst(implicit p: Parameters) extends BufferedGrant()(p) with HasClientId
/** Contains definitions of the the built-in grant types and factories /** Contains definitions of the the built-in grant types and factories
* for [[uncore.Grant]] and [[uncore.GrantToDst]] * for [[uncore.Grant]] and [[uncore.GrantToDst]]
* *
@ -1491,17 +1528,24 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
data = Bits(0)) data = Bits(0))
} }
class TileLinkIONarrower(factor: Int) extends TLModule { class TileLinkIONarrower(innerTLId: String, outerTLId: String)(implicit p: Parameters) extends Module {
val outerParams = params.alterPartial({ val innerParams = p(TLKey(innerTLId))
case TLDataBeats => tlDataBeats * factor val outerParams = p(TLKey(outerTLId))
}) val innerDataBeats = innerParams.dataBeats
val outerDataBeats = outerParams(TLDataBeats) val innerDataBits = innerParams.dataBitsPerBeat
val outerDataBits = outerParams(TLDataBits) val innerWriteMaskBits = innerParams.writeMaskBits
val outerWriteMaskBits = outerParams(TLWriteMaskBits) val outerDataBeats = outerParams.dataBeats
val outerDataBits = outerParams.dataBitsPerBeat
val outerWriteMaskBits = outerParams.writeMaskBits
require(outerDataBeats >= innerDataBeats)
require(outerDataBeats % innerDataBeats == 0)
require(outerDataBits >= innerDataBits)
val factor = outerDataBeats / innerDataBeats
val io = new Bundle { val io = new Bundle {
val in = new ClientUncachedTileLinkIO().flip val in = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => innerTLId})).flip
val out = Bundle(new ClientUncachedTileLinkIO)(outerParams) val out = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => outerTLId}))
} }
if (factor > 1) { if (factor > 1) {
@ -1511,8 +1555,8 @@ class TileLinkIONarrower(factor: Int) extends TLModule {
val stretch = iacq.a_type === Acquire.putBlockType val stretch = iacq.a_type === Acquire.putBlockType
val shrink = iacq.a_type === Acquire.getBlockType val shrink = iacq.a_type === Acquire.getBlockType
val acq_data_buffer = Reg(UInt(width = tlDataBits)) val acq_data_buffer = Reg(UInt(width = innerDataBits))
val acq_wmask_buffer = Reg(UInt(width = tlWriteMaskBits)) val acq_wmask_buffer = Reg(UInt(width = innerWriteMaskBits))
val acq_client_id = Reg(iacq.client_xact_id) val acq_client_id = Reg(iacq.client_xact_id)
val acq_addr_block = Reg(iacq.addr_block) val acq_addr_block = Reg(iacq.addr_block)
val acq_addr_beat = Reg(iacq.addr_beat) val acq_addr_beat = Reg(iacq.addr_beat)
@ -1560,7 +1604,7 @@ class TileLinkIONarrower(factor: Int) extends TLModule {
val gnt_client_id = Reg(ognt.client_xact_id) val gnt_client_id = Reg(ognt.client_xact_id)
val gnt_manager_id = Reg(ognt.manager_xact_id) val gnt_manager_id = Reg(ognt.manager_xact_id)
val ignt_ctr = Counter(tlDataBeats) val ignt_ctr = Counter(innerDataBeats)
val ognt_ctr = Counter(factor) val ognt_ctr = Counter(factor)
val sending_get = Reg(init = Bool(false)) val sending_get = Reg(init = Bool(false))

32
uncore/src/main/scala/uncore.scala
View File

@ -7,23 +7,31 @@ case object NReleaseTransactors extends Field[Int]
case object NProbeTransactors extends Field[Int] case object NProbeTransactors extends Field[Int]
case object NAcquireTransactors extends Field[Int] case object NAcquireTransactors extends Field[Int]
/** Identifies the TLId of the inner network in a hierarchical cache controller */
case object InnerTLId extends Field[String]
/** Identifies the TLId of the outer network in a hierarchical cache controller */
case object OuterTLId extends Field[String]
trait HasCoherenceAgentParameters { trait HasCoherenceAgentParameters {
implicit val p: Parameters implicit val p: Parameters
val nReleaseTransactors = 1 val nReleaseTransactors = 1
val nAcquireTransactors = p(NAcquireTransactors) val nAcquireTransactors = p(NAcquireTransactors)
val nTransactors = nReleaseTransactors + nAcquireTransactors val nTransactors = nReleaseTransactors + nAcquireTransactors
val outerTLParams = p.alterPartial({ case TLId => p(OuterTLId)}) val outerTLId = p(OuterTLId)
val outerDataBeats = outerTLParams(TLDataBeats) val outerTLParams = p(TLKey(outerTLId))
val outerDataBits = outerTLParams(TLDataBits) val outerDataBeats = outerTLParams.dataBeats
val outerDataBits = outerTLParams.dataBits
val outerBeatAddrBits = log2Up(outerDataBeats) val outerBeatAddrBits = log2Up(outerDataBeats)
val outerByteAddrBits = log2Up(outerDataBits/8) val outerByteAddrBits = log2Up(outerDataBits/8)
val innerTLParams = p.alterPartial({case TLId => p(InnerTLId)}) val outerWriteMaskBits = outerTLParams.writeMaskBits
val innerDataBeats = innerTLParams(TLDataBeats) val innerTLId = p(InnerTLId)
val innerDataBits = innerTLParams(TLDataBits) val innerTLParams = p(TLKey(innerTLId))
val innerWriteMaskBits = innerTLParams(TLWriteMaskBits) val innerDataBeats = innerTLParams.dataBeats
val innerDataBits = innerTLParams.dataBits
val innerWriteMaskBits = innerTLParams.writeMaskBits
val innerBeatAddrBits = log2Up(innerDataBeats) val innerBeatAddrBits = log2Up(innerDataBeats)
val innerByteAddrBits = log2Up(innerDataBits/8) val innerByteAddrBits = log2Up(innerDataBits/8)
require(outerDataBeats == innerDataBeats) //TODO: must fix all xact_data Vecs to remove this requirement require(outerDataBeats == innerDataBeats) //TODO: fix all xact_data Vecs to remove this requirement
} }
abstract class CoherenceAgentModule(implicit val p: Parameters) extends Module abstract class CoherenceAgentModule(implicit val p: Parameters) extends Module
@ -52,7 +60,7 @@ trait HasCoherenceAgentWiringHelpers {
} }
trait HasInnerTLIO extends HasCoherenceAgentParameters { trait HasInnerTLIO extends HasCoherenceAgentParameters {
val inner = Bundle(new ManagerTileLinkIO)(innerTLParams) val inner = Bundle(new ManagerTileLinkIO()(p.alterPartial({case TLId => p(InnerTLId)})))
val incoherent = Vec(Bool(), inner.tlNCachingClients).asInput val incoherent = Vec(Bool(), inner.tlNCachingClients).asInput
def iacq(dummy: Int = 0) = inner.acquire.bits def iacq(dummy: Int = 0) = inner.acquire.bits
def iprb(dummy: Int = 0) = inner.probe.bits def iprb(dummy: Int = 0) = inner.probe.bits
@ -62,13 +70,13 @@ trait HasInnerTLIO extends HasCoherenceAgentParameters {
} }
trait HasUncachedOuterTLIO extends HasCoherenceAgentParameters { trait HasUncachedOuterTLIO extends HasCoherenceAgentParameters {
val outer = Bundle(new ClientUncachedTileLinkIO)(outerTLParams) val outer = Bundle(new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => p(OuterTLId)})))
def oacq(dummy: Int = 0) = outer.acquire.bits def oacq(dummy: Int = 0) = outer.acquire.bits
def ognt(dummy: Int = 0) = outer.grant.bits def ognt(dummy: Int = 0) = outer.grant.bits
} }
trait HasCachedOuterTLIO extends HasCoherenceAgentParameters { trait HasCachedOuterTLIO extends HasCoherenceAgentParameters {
val outer = Bundle(new ClientTileLinkIO)(outerTLParams) val outer = Bundle(new ClientTileLinkIO()(p.alterPartial({case TLId => p(OuterTLId)})))
def oacq(dummy: Int = 0) = outer.acquire.bits def oacq(dummy: Int = 0) = outer.acquire.bits
def oprb(dummy: Int = 0) = outer.probe.bits def oprb(dummy: Int = 0) = outer.probe.bits
def orel(dummy: Int = 0) = outer.release.bits def orel(dummy: Int = 0) = outer.release.bits
@ -89,7 +97,7 @@ abstract class ManagerCoherenceAgent(implicit p: Parameters) extends CoherenceAg
with HasCoherenceAgentWiringHelpers { with HasCoherenceAgentWiringHelpers {
val io = new ManagerTLIO val io = new ManagerTLIO
def innerTL = io.inner def innerTL = io.inner
def outerTL = TileLinkIOWrapper(io.outer)(outerTLParams) def outerTL = TileLinkIOWrapper(io.outer)(p.alterPartial({case TLId => p(OuterTLId)}))
def incoherent = io.incoherent def incoherent = io.incoherent
} }