riscv/rocket-chip
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[debug] rocket: fix for issue 121, correct debug ROM and stall logic

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This commit is contained in:
Megan Wachs 2016-06-02 18:35:17 -07:00 committed by Andrew Waterman
parent 2e88ffc364
commit 7e550ab07c
1 changed files with 7 additions and 4 deletions
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11
uncore/src/main/scala/debug.scala
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@ -214,9 +214,13 @@ class DefaultDebugModuleConfig (val ncomponents : Int, val xlen:Int)
extends DebugModuleConfig( extends DebugModuleConfig(
nComponents = ncomponents, nComponents = ncomponents,
nDebugBusAddrSize = 5, nDebugBusAddrSize = 5,
// While smaller numbers are theoretically
// possible as noted in the Spec,
// the ROM image would need to be
// adjusted accordingly.
nDebugRamBytes = xlen match{ nDebugRamBytes = xlen match{
case 32 => 28 case 32 => 64
case 64 => 40 case 64 => 64
case 128 => 64 case 128 => 64
}, },
debugRomContents = Some(DsbBusConsts.defaultRomContents), debugRomContents = Some(DsbBusConsts.defaultRomContents),
@ -888,8 +892,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
Acquire.getType, Acquire.getBlockType, Acquire.putType, Acquire.putBlockType Acquire.getType, Acquire.getBlockType, Acquire.putType, Acquire.putBlockType
).map(sbAcqReg.isBuiltInType _) ).map(sbAcqReg.isBuiltInType _)
val sbMultibeat = sbReg_getblk val sbMultibeat = sbReg_getblk & sbAcqValidReg;
val sbBeatInc1 = sbAcqReg.addr_beat + UInt(1) val sbBeatInc1 = sbAcqReg.addr_beat + UInt(1)