First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.

src/main/scala/uncore/converters/Smi.scala

@@ -30,3 +30,30 @@ class SmiIOTileLinkIOConverter(val dataWidth: Int, val addrWidth: Int)
   decoupledNastiConnect(nasti2smi.io.nasti, tl2nasti.io.nasti)
   io.smi <> nasti2smi.io.smi
 }
+
+class SmiConverterTest(implicit val p: Parameters) extends unittest.UnitTest
+    with HasTileLinkParameters {
+  val outermostParams = p.alterPartial({ case TLId => "Outermost" })
+
+  val smiWidth = 32
+  val smiDepth = 64
+  val tlDepth = (smiWidth * smiDepth) / tlDataBits
+
+  val smimem = Module(new SmiMem(smiWidth, smiDepth))
+  val conv = Module(new SmiIOTileLinkIOConverter(
+    smiWidth, log2Up(smiDepth))(outermostParams))
+  val driver = Module(new DriverSet(
+    (driverParams: Parameters) => {
+      implicit val p = driverParams
+      Seq(
+        Module(new PutSweepDriver(tlDepth)),
+        Module(new PutMaskDriver(smiWidth / 8)),
+        Module(new PutBlockSweepDriver(tlDepth / tlDataBeats)),
+        Module(new GetMultiWidthDriver))
+    })(outermostParams))
+
+  conv.io.tl <> driver.io.mem
+  smimem.io <> conv.io.smi
+  driver.io.start := io.start
+  io.finished := driver.io.finished
+}

src/main/scala/uncore/devices/Bram.scala

@@ -2,6 +2,7 @@ package uncore.devices
 
 import Chisel._
 import cde.{Parameters, Field}
+import unittest.UnitTest
 import junctions._
 import uncore.tilelink._
 import uncore.util._
@@ -159,3 +160,24 @@ class TileLinkTestRAM(depth: Int)(implicit val p: Parameters) extends Module
     ram(acq_addr) := (old_data & ~wmask) | (result & wmask)
   }
 }
+
+class TileLinkRAMTest(implicit val p: Parameters)
+    extends UnitTest with HasTileLinkParameters {
+
+  val depth = 2 * tlDataBeats
+  val ram = Module(new TileLinkTestRAM(depth))
+  val driver = Module(new DriverSet(
+    (driverParams: Parameters) => {
+      implicit val p = driverParams
+      Seq(
+        Module(new PutSweepDriver(depth)),
+        Module(new PutMaskDriver),
+        Module(new PutAtomicDriver),
+        Module(new PutBlockSweepDriver(depth / tlDataBeats)),
+        Module(new PrefetchDriver),
+        Module(new GetMultiWidthDriver))
+    }))
+  ram.io <> driver.io.mem
+  driver.io.start := io.start
+  io.finished := driver.io.finished
+}

src/main/scala/uncore/devices/Rom.scala

@@ -1,6 +1,7 @@
 package uncore.devices
 
 import Chisel._
+import unittest.UnitTest
 import junctions._
 import uncore.tilelink._
 import uncore.util._
@@ -41,6 +42,26 @@ class ROMSlave(contents: Seq[Byte])(implicit val p: Parameters) extends Module
     data = rdata)
 }
 
+class ROMSlaveTest(implicit p: Parameters) extends UnitTest {
+  implicit val testName = "ROMSlaveTest"
+  val romdata = Seq(
+    BigInt("01234567deadbeef", 16),
+    BigInt("ab32fee8d00dfeed", 16))
+  val rombytes = romdata.map(_.toByteArray.reverse).flatten
+  val rom = Module(new ROMSlave(rombytes))
+  val driver = Module(new DriverSet(
+    (driverParams: Parameters) => {
+      implicit val p = driverParams
+      Seq(
+        Module(new GetMultiWidthDriver),
+        Module(new GetSweepDriver(romdata)),
+        Module(new GetBlockSweepDriver(romdata)))
+    }))
+  rom.io <> driver.io.mem
+  driver.io.start := io.start
+  io.finished := driver.io.finished
+}
+
 class NastiROM(contents: Seq[Byte])(implicit p: Parameters) extends Module {
   val io = new NastiIO().flip
   val ar = Queue(io.ar, 1)

src/main/scala/uncore/tilelink/Drivers.scala

@@ -1,8 +1,7 @@
-package uncore.unittests
+package uncore.tilelink
 
 import Chisel._
 import junctions._
-import uncore.tilelink._
 import uncore.constants._
 import uncore.util._
 import cde.Parameters

src/main/scala/uncore/tilelink2/Fuzzer.scala

@@ -3,7 +3,7 @@ package uncore.tilelink2
 
 import Chisel._
 import chisel3.util.LFSR16
-import junctions.unittests._
+import unittest._
 
 class IDMapGenerator(numIds: Int) extends Module {
   val w = log2Up(numIds)

src/main/scala/uncore/unittests/Tests.scala

@@ -1,86 +0,0 @@
-package uncore.unittests
-
-import Chisel._
-import junctions._
-import junctions.unittests._
-import uncore.devices._
-import uncore.tilelink._
-import uncore.converters._
-import cde.Parameters
-
-class SmiConverterTest(implicit val p: Parameters) extends UnitTest
-    with HasTileLinkParameters {
-  val outermostParams = p.alterPartial({ case TLId => "Outermost" })
-
-  val smiWidth = 32
-  val smiDepth = 64
-  val tlDepth = (smiWidth * smiDepth) / tlDataBits
-
-  val smimem = Module(new SmiMem(smiWidth, smiDepth))
-  val conv = Module(new SmiIOTileLinkIOConverter(
-    smiWidth, log2Up(smiDepth))(outermostParams))
-  val driver = Module(new DriverSet(
-    (driverParams: Parameters) => {
-      implicit val p = driverParams
-      Seq(
-        Module(new PutSweepDriver(tlDepth)),
-        Module(new PutMaskDriver(smiWidth / 8)),
-        Module(new PutBlockSweepDriver(tlDepth / tlDataBeats)),
-        Module(new GetMultiWidthDriver))
-    })(outermostParams))
-
-  conv.io.tl <> driver.io.mem
-  smimem.io <> conv.io.smi
-  driver.io.start := io.start
-  io.finished := driver.io.finished
-}
-
-class ROMSlaveTest(implicit p: Parameters) extends UnitTest {
-  implicit val testName = "ROMSlaveTest"
-  val romdata = Seq(
-    BigInt("01234567deadbeef", 16),
-    BigInt("ab32fee8d00dfeed", 16))
-  val rombytes = romdata.map(_.toByteArray.reverse).flatten
-  val rom = Module(new ROMSlave(rombytes))
-  val driver = Module(new DriverSet(
-    (driverParams: Parameters) => {
-      implicit val p = driverParams
-      Seq(
-        Module(new GetMultiWidthDriver),
-        Module(new GetSweepDriver(romdata)),
-        Module(new GetBlockSweepDriver(romdata)))
-    }))
-  rom.io <> driver.io.mem
-  driver.io.start := io.start
-  io.finished := driver.io.finished
-}
-
-class TileLinkRAMTest(implicit val p: Parameters)
-    extends UnitTest with HasTileLinkParameters {
-
-  val depth = 2 * tlDataBeats
-  val ram = Module(new TileLinkTestRAM(depth))
-  val driver = Module(new DriverSet(
-    (driverParams: Parameters) => {
-      implicit val p = driverParams
-      Seq(
-        Module(new PutSweepDriver(depth)),
-        Module(new PutMaskDriver),
-        Module(new PutAtomicDriver),
-        Module(new PutBlockSweepDriver(depth / tlDataBeats)),
-        Module(new PrefetchDriver),
-        Module(new GetMultiWidthDriver))
-    }))
-  ram.io <> driver.io.mem
-  driver.io.start := io.start
-  io.finished := driver.io.finished
-}
-
-object UncoreUnitTests {
-  def apply(implicit p: Parameters): Seq[UnitTest] =
-    Seq(
-      Module(new SmiConverterTest),
-      Module(new ROMSlaveTest),
-      Module(new TileLinkRAMTest),
-      Module(new uncore.tilelink2.TLFuzzRAMTest))
-}