60 lines
1.8 KiB
Scala
60 lines
1.8 KiB
Scala
// See LICENSE for details
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package uncore.converters
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import Chisel._
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import junctions._
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import uncore.tilelink._
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import cde.Parameters
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/** Convert TileLink protocol to Smi protocol */
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class SmiIOTileLinkIOConverter(val dataWidth: Int, val addrWidth: Int)
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(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val tl = (new ClientUncachedTileLinkIO).flip
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val smi = new SmiIO(dataWidth, addrWidth)
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}
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def decoupledNastiConnect(outer: NastiIO, inner: NastiIO) {
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outer.ar <> Queue(inner.ar)
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outer.aw <> Queue(inner.aw)
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outer.w <> Queue(inner.w)
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inner.r <> Queue(outer.r)
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inner.b <> Queue(outer.b)
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}
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val tl2nasti = Module(new NastiIOTileLinkIOConverter())
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val nasti2smi = Module(new SmiIONastiIOConverter(dataWidth, addrWidth))
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tl2nasti.io.tl <> io.tl
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decoupledNastiConnect(nasti2smi.io.nasti, tl2nasti.io.nasti)
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io.smi <> nasti2smi.io.smi
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}
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class SmiConverterTest(implicit val p: Parameters) extends unittest.UnitTest
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with HasTileLinkParameters {
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val outermostParams = p.alterPartial({ case TLId => "Outermost" })
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val smiWidth = 32
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val smiDepth = 64
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val tlDepth = (smiWidth * smiDepth) / tlDataBits
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val smimem = Module(new SmiMem(smiWidth, smiDepth))
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val conv = Module(new SmiIOTileLinkIOConverter(
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smiWidth, log2Up(smiDepth))(outermostParams))
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val driver = Module(new DriverSet(
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(driverParams: Parameters) => {
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implicit val p = driverParams
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Seq(
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Module(new PutSweepDriver(tlDepth)),
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Module(new PutMaskDriver(smiWidth / 8)),
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Module(new PutBlockSweepDriver(tlDepth / tlDataBeats)),
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Module(new GetMultiWidthDriver))
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})(outermostParams))
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conv.io.tl <> driver.io.mem
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smimem.io <> conv.io.smi
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driver.io.start := io.start
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io.finished := driver.io.finished
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}
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