rocketchip: include an socBus between l1tol2 and periphery (#415)

Sometimes we have high performance devices that go inbetween.

src/main/scala/rocketchip/BaseTop.scala

@@ -31,9 +31,10 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
 
   TLImp.emitMonitors = q(TLEmitMonitors)
 
-  // Add a peripheral bus
+  // Add a SoC and peripheral bus
+  val socBus = LazyModule(new TLXbar)
   val peripheryBus = LazyModule(new TLXbar)
-  lazy val peripheryManagers = peripheryBus.node.edgesIn(0).manager.managers
+  lazy val peripheryManagers = socBus.node.edgesIn(0).manager.managers
 
   lazy val c = CoreplexConfig(
     nTiles = q(NTiles),
@@ -54,11 +55,15 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
   val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
 
   peripheryBus.node :=
-    TLWidthWidget(legacy.tlDataBytes)(
+    TLWidthWidget(p(SOCBusKey).beatBytes)(
     TLBuffer()(
     TLAtomicAutomata(arithmetic = p(PeripheryBusKey).arithAMO)(
+    socBus.node)))
+
+  socBus.node :=
+    TLWidthWidget(legacy.tlDataBytes)(
     TLHintHandler()(
-    legacy.node))))
+    legacy.node))
 
   TopModule.contents = Some(this)
 }

src/main/scala/rocketchip/Configs.scala

@@ -43,6 +43,7 @@ class BasePlatformConfig extends Config(
         case BuildCoreplex =>
           (c: CoreplexConfig, p: Parameters) => LazyModule(new DefaultCoreplex(c)(p)).module
         case NExtTopInterrupts => 2
+        case SOCBusKey => SOCBusConfig(beatBytes = site(TLKey("L2toMMIO")).dataBitsPerBeat/8)
         case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 4)
         // Note that PLIC asserts that this is > 0.
         case AsyncDebugBus => false

src/main/scala/rocketchip/Periphery.scala

@@ -51,6 +51,9 @@ case object RTCPeriod extends Field[Int]
 /* Specifies the periphery bus configuration */
 case class PeripheryBusConfig(arithAMO: Boolean, beatBytes: Int = 4)
 case object PeripheryBusKey extends Field[PeripheryBusConfig]
+/* Specifies the SOC-bus configuration */
+case class SOCBusConfig(beatBytes: Int = 4)
+case object SOCBusKey extends Field[SOCBusConfig]
 
 /* Specifies the data and id width at the chip boundary */
 case object EdgeDataBits extends Field[Int]
@@ -91,6 +94,7 @@ trait HasPeripheryParameters {
   lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" })
   lazy val edgeMMIOParams = p.alterPartial({ case TLId => "MMIOtoEdge" })
   lazy val peripheryBusConfig = p(PeripheryBusKey)
+  lazy val socBusConfig = p(SOCBusKey)
   lazy val cacheBlockBytes = p(CacheBlockBytes)
 }