From 7dc97674d6e8cce3ba7f4f9204d5bbb7550bd2cc Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Mon, 24 Oct 2016 23:56:09 -0700
Subject: [PATCH] rocketchip: include an socBus between l1tol2 and periphery
 (#415)

Sometimes we have high performance devices that go inbetween.
---
 src/main/scala/rocketchip/BaseTop.scala   | 13 +++++++++----
 src/main/scala/rocketchip/Configs.scala   |  1 +
 src/main/scala/rocketchip/Periphery.scala |  4 ++++
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index 159fd159..a7d9836f 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -31,9 +31,10 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
 
   TLImp.emitMonitors = q(TLEmitMonitors)
 
-  // Add a peripheral bus
+  // Add a SoC and peripheral bus
+  val socBus = LazyModule(new TLXbar)
   val peripheryBus = LazyModule(new TLXbar)
-  lazy val peripheryManagers = peripheryBus.node.edgesIn(0).manager.managers
+  lazy val peripheryManagers = socBus.node.edgesIn(0).manager.managers
 
   lazy val c = CoreplexConfig(
     nTiles = q(NTiles),
@@ -54,11 +55,15 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
   val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
 
   peripheryBus.node :=
-    TLWidthWidget(legacy.tlDataBytes)(
+    TLWidthWidget(p(SOCBusKey).beatBytes)(
     TLBuffer()(
     TLAtomicAutomata(arithmetic = p(PeripheryBusKey).arithAMO)(
+    socBus.node)))
+
+  socBus.node :=
+    TLWidthWidget(legacy.tlDataBytes)(
     TLHintHandler()(
-    legacy.node))))
+    legacy.node))
 
   TopModule.contents = Some(this)
 }
diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala
index 90f48711..e253bfb5 100644
--- a/src/main/scala/rocketchip/Configs.scala
+++ b/src/main/scala/rocketchip/Configs.scala
@@ -43,6 +43,7 @@ class BasePlatformConfig extends Config(
         case BuildCoreplex =>
           (c: CoreplexConfig, p: Parameters) => LazyModule(new DefaultCoreplex(c)(p)).module
         case NExtTopInterrupts => 2
+        case SOCBusKey => SOCBusConfig(beatBytes = site(TLKey("L2toMMIO")).dataBitsPerBeat/8)
         case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 4)
         // Note that PLIC asserts that this is > 0.
         case AsyncDebugBus => false
diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index 023f9e5e..f1d3d477 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -51,6 +51,9 @@ case object RTCPeriod extends Field[Int]
 /* Specifies the periphery bus configuration */
 case class PeripheryBusConfig(arithAMO: Boolean, beatBytes: Int = 4)
 case object PeripheryBusKey extends Field[PeripheryBusConfig]
+/* Specifies the SOC-bus configuration */
+case class SOCBusConfig(beatBytes: Int = 4)
+case object SOCBusKey extends Field[SOCBusConfig]
 
 /* Specifies the data and id width at the chip boundary */
 case object EdgeDataBits extends Field[Int]
@@ -91,6 +94,7 @@ trait HasPeripheryParameters {
   lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" })
   lazy val edgeMMIOParams = p.alterPartial({ case TLId => "MMIOtoEdge" })
   lazy val peripheryBusConfig = p(PeripheryBusKey)
+  lazy val socBusConfig = p(SOCBusKey)
   lazy val cacheBlockBytes = p(CacheBlockBytes)
 }