riscv/rocket-chip
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rocketchip: include an socBus between l1tol2 and periphery (#415)

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Sometimes we have high performance devices that go inbetween.
This commit is contained in:
Wesley W. Terpstra
2016-10-24 23:56:09 -07:00
committed by GitHub
parent a5ac106bb8
commit 7dc97674d6
3 changed files with 14 additions and 4 deletions
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13
src/main/scala/rocketchip/BaseTop.scala
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@@ -31,9 +31,10 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
TLImp.emitMonitors = q(TLEmitMonitors) TLImp.emitMonitors = q(TLEmitMonitors)
// Add a peripheral bus // Add a SoC and peripheral bus
val socBus = LazyModule(new TLXbar)
val peripheryBus = LazyModule(new TLXbar) val peripheryBus = LazyModule(new TLXbar)
lazy val peripheryManagers = peripheryBus.node.edgesIn(0).manager.managers lazy val peripheryManagers = socBus.node.edgesIn(0).manager.managers
lazy val c = CoreplexConfig( lazy val c = CoreplexConfig(
nTiles = q(NTiles), nTiles = q(NTiles),
@@ -54,11 +55,15 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" }))) val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
peripheryBus.node := peripheryBus.node :=
TLWidthWidget(legacy.tlDataBytes)( TLWidthWidget(p(SOCBusKey).beatBytes)(
TLBuffer()( TLBuffer()(
TLAtomicAutomata(arithmetic = p(PeripheryBusKey).arithAMO)( TLAtomicAutomata(arithmetic = p(PeripheryBusKey).arithAMO)(
socBus.node)))
socBus.node :=
TLWidthWidget(legacy.tlDataBytes)(
TLHintHandler()( TLHintHandler()(
legacy.node)))) legacy.node))
TopModule.contents = Some(this) TopModule.contents = Some(this)
} }

1
src/main/scala/rocketchip/Configs.scala
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@@ -43,6 +43,7 @@ class BasePlatformConfig extends Config(
case BuildCoreplex => case BuildCoreplex =>
(c: CoreplexConfig, p: Parameters) => LazyModule(new DefaultCoreplex(c)(p)).module (c: CoreplexConfig, p: Parameters) => LazyModule(new DefaultCoreplex(c)(p)).module
case NExtTopInterrupts => 2 case NExtTopInterrupts => 2
case SOCBusKey => SOCBusConfig(beatBytes = site(TLKey("L2toMMIO")).dataBitsPerBeat/8)
case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 4) case PeripheryBusKey => PeripheryBusConfig(arithAMO = true, beatBytes = 4)
// Note that PLIC asserts that this is > 0. // Note that PLIC asserts that this is > 0.
case AsyncDebugBus => false case AsyncDebugBus => false

4
src/main/scala/rocketchip/Periphery.scala
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@@ -51,6 +51,9 @@ case object RTCPeriod extends Field[Int]
/* Specifies the periphery bus configuration */ /* Specifies the periphery bus configuration */
case class PeripheryBusConfig(arithAMO: Boolean, beatBytes: Int = 4) case class PeripheryBusConfig(arithAMO: Boolean, beatBytes: Int = 4)
case object PeripheryBusKey extends Field[PeripheryBusConfig] case object PeripheryBusKey extends Field[PeripheryBusConfig]
/* Specifies the SOC-bus configuration */
case class SOCBusConfig(beatBytes: Int = 4)
case object SOCBusKey extends Field[SOCBusConfig]
/* Specifies the data and id width at the chip boundary */ /* Specifies the data and id width at the chip boundary */
case object EdgeDataBits extends Field[Int] case object EdgeDataBits extends Field[Int]
@@ -91,6 +94,7 @@ trait HasPeripheryParameters {
lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" }) lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" })
lazy val edgeMMIOParams = p.alterPartial({ case TLId => "MMIOtoEdge" }) lazy val edgeMMIOParams = p.alterPartial({ case TLId => "MMIOtoEdge" })
lazy val peripheryBusConfig = p(PeripheryBusKey) lazy val peripheryBusConfig = p(PeripheryBusKey)
lazy val socBusConfig = p(SOCBusKey)
lazy val cacheBlockBytes = p(CacheBlockBytes) lazy val cacheBlockBytes = p(CacheBlockBytes)
} }