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rocketchip: include an socBus between l1tol2 and periphery (#415)

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Sometimes we have high performance devices that go inbetween.
This commit is contained in:
Wesley W. Terpstra
2016-10-24 23:56:09 -07:00
committed by GitHub
parent a5ac106bb8
commit 7dc97674d6
3 changed files with 14 additions and 4 deletions
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4
src/main/scala/rocketchip/Periphery.scala
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@ -51,6 +51,9 @@ case object RTCPeriod extends Field[Int]
/* Specifies the periphery bus configuration */
case class PeripheryBusConfig(arithAMO: Boolean, beatBytes: Int = 4)
case object PeripheryBusKey extends Field[PeripheryBusConfig]
/* Specifies the SOC-bus configuration */
case class SOCBusConfig(beatBytes: Int = 4)
case object SOCBusKey extends Field[SOCBusConfig]
/* Specifies the data and id width at the chip boundary */
case object EdgeDataBits extends Field[Int]
@ -91,6 +94,7 @@ trait HasPeripheryParameters {
lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" })
lazy val edgeMMIOParams = p.alterPartial({ case TLId => "MMIOtoEdge" })
lazy val peripheryBusConfig = p(PeripheryBusKey)
lazy val socBusConfig = p(SOCBusKey)
lazy val cacheBlockBytes = p(CacheBlockBytes)
}