riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

rocketchip: include an socBus between l1tol2 and periphery (#415)

Browse Source 
Sometimes we have high performance devices that go inbetween.
This commit is contained in:
Wesley W. Terpstra
2016-10-24 23:56:09 -07:00
committed by GitHub
parent a5ac106bb8
commit 7dc97674d6
3 changed files with 14 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/main/scala/rocketchip/BaseTop.scala
View File

@@ -31,9 +31,10 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
TLImp.emitMonitors = q(TLEmitMonitors)
// Add a peripheral bus
// Add a SoC and peripheral bus
val socBus = LazyModule(new TLXbar)
val peripheryBus = LazyModule(new TLXbar)
lazy val peripheryManagers = peripheryBus.node.edgesIn(0).manager.managers
lazy val peripheryManagers = socBus.node.edgesIn(0).manager.managers
lazy val c = CoreplexConfig(
nTiles = q(NTiles),
@@ -54,11 +55,15 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
peripheryBus.node :=
TLWidthWidget(legacy.tlDataBytes)(
TLWidthWidget(p(SOCBusKey).beatBytes)(
TLBuffer()(
TLAtomicAutomata(arithmetic = p(PeripheryBusKey).arithAMO)(
socBus.node)))
socBus.node :=
TLWidthWidget(legacy.tlDataBytes)(
TLHintHandler()(
legacy.node))))
legacy.node))
TopModule.contents = Some(this)
}