riscv/rocket-chip
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Initial commit for the hwacha reference-chip/rocket re-integration.

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This commit is contained in:
Stephen Twigg
2013-10-30 20:44:02 -07:00
parent 04108270ff
commit 7da65434ee
2 changed files with 6 additions and 2 deletions
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5
src/main/scala/RocketChip.scala
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@ -254,8 +254,11 @@ class Top extends Module {
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16)
val dc = DCacheConfig(128, 4, ntlb = 8,
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
val hc = hwacha.HwachaConfiguration(8, 256)
val rc = RocketConfiguration(tl, ic, dc,
fpu = HAS_FPU)
fpu = HAS_FPU,
rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
)
val io = new VLSITopIO(HTIF_WIDTH)