From 7da65434ee44682df4d0901e6abbfe87a7d0b6a9 Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Wed, 30 Oct 2013 20:44:02 -0700 Subject: [PATCH] Initial commit for the hwacha reference-chip/rocket re-integration. --- project/build.scala | 3 ++- src/main/scala/RocketChip.scala | 5 ++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/project/build.scala b/project/build.scala index 5bf99b3c..9f244687 100644 --- a/project/build.scala +++ b/project/build.scala @@ -29,7 +29,8 @@ object BuildSettings extends Build { lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel) lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat) lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore) - lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket) + lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(uncore, rocket) + lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha) val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code") val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command") diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index d282d2b0..f80411b2 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -254,8 +254,11 @@ class Top extends Module { val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16) val dc = DCacheConfig(128, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) + val hc = hwacha.HwachaConfiguration(8, 256) val rc = RocketConfiguration(tl, ic, dc, - fpu = HAS_FPU) + fpu = HAS_FPU, + rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) + ) val io = new VLSITopIO(HTIF_WIDTH)