riscv/rocket-chip
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Revert "rocket: link dtim to its cpu"

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This reverts commit e6c2d446cc.
This commit is contained in:
Wesley W. Terpstra 2017-06-28 21:28:16 -07:00
parent fbcd6f0eb2
commit 7d6f8d48f2
2 changed files with 3 additions and 14 deletions
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3
src/main/scala/rocket/RocketTiles.scala
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@ -89,9 +89,6 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb) ++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb)
} }
} }
override def dtimOwner = Some(cpuDevice)
val intcDevice = new Device { val intcDevice = new Device {
def describe(resources: ResourceBindings): Description = { def describe(resources: ResourceBindings): Description = {
Description(s"cpus/cpu@${hartid}/interrupt-controller", Map( Description(s"cpus/cpu@${hartid}/interrupt-controller", Map(

14
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -13,16 +13,9 @@ import uncore.tilelink2._
import uncore.util._ import uncore.util._
import util._ import util._
class ScratchpadSlavePort(address: AddressSet, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule
with HasCoreParameters { with HasCoreParameters {
val device = new SimpleDevice("dtim", Seq("sifive,dtim0")) { val device = new SimpleDevice("dtim", Seq("sifive,dtim0"))
override def describe(resources: ResourceBindings): Description = {
val extra = owner.map(x => ("sifive,cpu" -> Seq(ResourceReference(x.label))))
val Description(name, mapping) = super.describe(resources)
Description(name, mapping ++ extra)
}
}
val node = TLManagerNode(Seq(TLManagerPortParameters( val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters( Seq(TLManagerParameters(
address = List(address), address = List(address),
@ -109,7 +102,6 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCor
val module: CanHaveScratchpadModule val module: CanHaveScratchpadModule
val slaveNode = TLInputNode() // Up to two uses for this input node: val slaveNode = TLInputNode() // Up to two uses for this input node:
def dtimOwner: Option[Device] = None // who owns the Scratchpad?
// 1) Frontend always exists, but may or may not have a scratchpad node // 1) Frontend always exists, but may or may not have a scratchpad node
val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), earlyAck=true)) val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), earlyAck=true))
@ -120,7 +112,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCor
// 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad // 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad
val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s => val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s =>
LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), dtimOwner)))) LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1)))))
scratch foreach { lm => lm.node := TLFragmenter(xLen/8, p(CacheBlockBytes), earlyAck=true)(slaveNode) } scratch foreach { lm => lm.node := TLFragmenter(xLen/8, p(CacheBlockBytes), earlyAck=true)(slaveNode) }
def findScratchpadFromICache: Option[AddressSet] = scratch.map { s => def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>