From 7d6f8d48f2d18c226f81c810d6e466b6de96f2ae Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 28 Jun 2017 21:28:16 -0700
Subject: [PATCH] Revert "rocket: link dtim to its cpu"

This reverts commit e6c2d446ccf85a409969e8b298fa5c6baca4ff4a.
---
 src/main/scala/rocket/RocketTiles.scala         |  3 ---
 src/main/scala/rocket/ScratchpadSlavePort.scala | 14 +++-----------
 2 files changed, 3 insertions(+), 14 deletions(-)

diff --git a/src/main/scala/rocket/RocketTiles.scala b/src/main/scala/rocket/RocketTiles.scala
index 4e5fccad..a393cb15 100644
--- a/src/main/scala/rocket/RocketTiles.scala
+++ b/src/main/scala/rocket/RocketTiles.scala
@@ -89,9 +89,6 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
         ++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb)
     }
   }
-
-  override def dtimOwner = Some(cpuDevice)
-
   val intcDevice = new Device {
     def describe(resources: ResourceBindings): Description = {
       Description(s"cpus/cpu@${hartid}/interrupt-controller", Map(
diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala
index 12035ee8..667cc157 100644
--- a/src/main/scala/rocket/ScratchpadSlavePort.scala
+++ b/src/main/scala/rocket/ScratchpadSlavePort.scala
@@ -13,16 +13,9 @@ import uncore.tilelink2._
 import uncore.util._
 import util._
 
-class ScratchpadSlavePort(address: AddressSet, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule
+class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule
     with HasCoreParameters {
-  val device = new SimpleDevice("dtim", Seq("sifive,dtim0")) {
-    override def describe(resources: ResourceBindings): Description = {
-      val extra = owner.map(x => ("sifive,cpu" -> Seq(ResourceReference(x.label))))
-      val Description(name, mapping) = super.describe(resources)
-      Description(name, mapping ++ extra)
-    }
-  }
-
+  val device = new SimpleDevice("dtim", Seq("sifive,dtim0"))
   val node = TLManagerNode(Seq(TLManagerPortParameters(
     Seq(TLManagerParameters(
       address            = List(address),
@@ -109,7 +102,6 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCor
   val module: CanHaveScratchpadModule
 
   val slaveNode = TLInputNode() // Up to two uses for this input node:
-  def dtimOwner: Option[Device] = None // who owns the Scratchpad?
 
   // 1) Frontend always exists, but may or may not have a scratchpad node
   val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), earlyAck=true))
@@ -120,7 +112,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCor
 
   // 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad
   val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s =>
-    LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), dtimOwner))))
+    LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1)))))
   scratch foreach { lm => lm.node := TLFragmenter(xLen/8, p(CacheBlockBytes), earlyAck=true)(slaveNode) }
 
   def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>