riscv/rocket-chip
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finished bit should be set true if generator not being used

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This commit is contained in:
Howard Mao 2015-11-11 18:51:16 -08:00
parent f93872d6b4
commit 7cae6cedf5
1 changed files with 1 additions and 1 deletions
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groundtest/src/main/scala/tile.scala
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@ -53,7 +53,7 @@ class GeneratorTile(id: Int, resetSignal: Bool)
} else {
io.uncached(0).acquire.valid := Bool(false)
io.uncached(0).grant.ready := Bool(false)
for (i <- 0 until nGensPerTile) { gen_finished(2 * i) := Bool(false) }
for (i <- 0 until nGensPerTile) { gen_finished(2 * i) := Bool(true) }
}
if (genCached) {