riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Correctly check for virtual-address canonicalization

Browse Source 
The previous check was necessary but not sufficient.
This commit is contained in:
Andrew Waterman 2018-01-02 18:41:25 -08:00
parent 7385c99435
commit 7c9a1b0265
1 changed files with 2 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/main/scala/rocket/RocketCore.scala
View File

@ -744,11 +744,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else { def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else {
// efficient means to compress 64-bit VA into vaddrBits+1 bits // efficient means to compress 64-bit VA into vaddrBits+1 bits
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1))
val a = a0 >> vaddrBits-1 val a = a0.asSInt >> vaddrBits
val e = ea(vaddrBits,vaddrBits-1).asSInt val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))
val msb =
Mux(a === UInt(0) || a === UInt(1), e =/= SInt(0),
Mux(a.asSInt === SInt(-1) || a.asSInt === SInt(-2), e === SInt(-1), e(0)))
Cat(msb, ea(vaddrBits-1,0)) Cat(msb, ea(vaddrBits-1,0))
} }