riscv/rocket-chip
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vector-vector add working!

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This commit is contained in:
Yunsup Lee 2012-02-15 02:28:07 -08:00
parent 6bdf9dc513
commit 7c11c1406c
3 changed files with 5 additions and 2 deletions
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3
rocket/src/main/scala/cpu.scala
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@ -141,6 +141,7 @@ class rocketProc extends Component
io.vimem.req_ppn := vitlb.io.cpu.resp_ppn io.vimem.req_ppn := vitlb.io.cpu.resp_ppn
io.vimem.req_val := vu.io.imem_req.valid io.vimem.req_val := vu.io.imem_req.valid
io.vimem.invalidate := ctrl.io.dpath.flush_inst io.vimem.invalidate := ctrl.io.dpath.flush_inst
vu.io.imem_req.ready := Bool(true)
vu.io.imem_resp.valid := io.vimem.resp_val vu.io.imem_resp.valid := io.vimem.resp_val
vu.io.imem_resp.bits := io.vimem.resp_data vu.io.imem_resp.bits := io.vimem.resp_data
// handle vitlb.io.cpu.exception // handle vitlb.io.cpu.exception
@ -149,6 +150,7 @@ class rocketProc extends Component
vu.io.vec_cmdq <> dpath.io.vcmdq vu.io.vec_cmdq <> dpath.io.vcmdq
vu.io.vec_ximm1q <> dpath.io.vximm1q vu.io.vec_ximm1q <> dpath.io.vximm1q
vu.io.vec_ximm2q <> dpath.io.vximm2q vu.io.vec_ximm2q <> dpath.io.vximm2q
vu.io.vec_ackq.ready := Bool(true)
ctrl.io.ext_mem.req_val := vu.io.dmem_req.valid ctrl.io.ext_mem.req_val := vu.io.dmem_req.valid
ctrl.io.ext_mem.req_cmd := vu.io.dmem_req.bits.cmd ctrl.io.ext_mem.req_cmd := vu.io.dmem_req.bits.cmd
@ -158,6 +160,7 @@ class rocketProc extends Component
dpath.io.ext_mem.req_idx := vu.io.dmem_req.bits.idx dpath.io.ext_mem.req_idx := vu.io.dmem_req.bits.idx
dpath.io.ext_mem.req_ppn := vu.io.dmem_req.bits.ppn dpath.io.ext_mem.req_ppn := vu.io.dmem_req.bits.ppn
dpath.io.ext_mem.req_data := vu.io.dmem_req.bits.data dpath.io.ext_mem.req_data := vu.io.dmem_req.bits.data
dpath.io.ext_mem.req_tag := vu.io.dmem_req.bits.tag
vu.io.dmem_resp.valid := dpath.io.ext_mem.resp_val vu.io.dmem_resp.valid := dpath.io.ext_mem.resp_val
vu.io.dmem_resp.bits.nack := ctrl.io.ext_mem.resp_nack vu.io.dmem_resp.bits.nack := ctrl.io.ext_mem.resp_nack

2
rocket/src/main/scala/ctrl.scala
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@ -764,7 +764,7 @@ class rocketCtrl extends Component
io.fpu.killx := kill_ex io.fpu.killx := kill_ex
io.fpu.killm := kill_mem io.fpu.killm := kill_mem
io.dtlb_val := ex_reg_mem_val; io.dtlb_val := ex_reg_mem_val || ex_reg_ext_mem_val;
io.dtlb_kill := mem_reg_kill; io.dtlb_kill := mem_reg_kill;
io.dmem.req_val := ex_reg_mem_val || ex_reg_ext_mem_val; io.dmem.req_val := ex_reg_mem_val || ex_reg_ext_mem_val;
io.dmem.req_kill := kill_dcache; io.dmem.req_kill := kill_dcache;

2
rocket/src/main/scala/dpath_vec.scala
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@ -174,7 +174,7 @@ class rocketDpathVec extends Component
Bits(0,20))))))) Bits(0,20)))))))
io.vximm1q.bits := io.vximm1q.bits :=
Mux(wb_sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, io.inst(21,10), vlenm1), Mux(wb_sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, io.inst(21,10), vlenm1(10,0)),
io.wdata) // VIMM_ALU io.wdata) // VIMM_ALU
io.vximm2q.bits := io.rs2 io.vximm2q.bits := io.rs2