riscv/rocket-chip
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support continous compilation via "make test"

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for c++ emulator only, for now
This commit is contained in:
Andrew Waterman 2012-11-17 19:58:18 -08:00
parent b58214d7e3
commit 7bcf59a18f
2 changed files with 28 additions and 34 deletions
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9
emulator/Makefile
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@ -12,11 +12,14 @@ CXXFLAGS := $(CXXFLAGS) -Itestbench -I$(basedir)/chisel/csrc -I../dramsim2
OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
CHISEL_ARGS := $(MODEL) --backend c --targetDir ../emulator/generated-src
CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd
generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(MODEL) --backend c --targetDir ../emulator/generated-src"
cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS)"
generated-src-debug/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(MODEL) --backend c --targetDir ../emulator/generated-src-debug --debug --vcd"
cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS_DEBUG)"
$(MODEL).o: %.o: generated-src/%.cpp
$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
@ -46,7 +49,7 @@ clean:
rm -rf *.o *.a emulator emulator-debug generated-src generated-src-debug DVEfiles output
test:
cd $(basedir)/sbt && $(SBT) "project referencechip" "~make ../emulator run-fast"
cd $(basedir)/sbt && $(SBT) "project referencechip" "~make ../emulator run-fast $(CHISEL_ARGS)"
#--------------------------------------------------------------------
# Run assembly tests and benchmarks

53
project/build.scala
View File

@ -8,22 +8,11 @@ object BuildSettings extends Build {
val buildVersion = "1.1"
val buildScalaVersion = "2.9.2"
val chiselDebug = SettingKey[Boolean]("chisel-debug", "generated backend sources with debug signals")
val chiselArgsDebug = SettingKey[Seq[String]]("chisel-args-debug", "additional chisel args for debug backend signals")
val chiselArgsC = SettingKey[Seq[String]]("chisel-args-c", "default chisel args for c backend")
val chiselArgsVlsi = SettingKey[Seq[String]]("chisel-args-vlsi", "default chisel args for vlsi backend")
val chiselArgsFpga = SettingKey[Seq[String]]("chisel-args-fpga", "default chisel args for fpga backend")
val buildSettings = Defaults.defaultSettings ++ Seq (
//unmanagedBase <<= baseDirectory { base => base / ".." / custom_lib" },
organization := buildOrganization,
version := buildVersion,
scalaVersion := buildScalaVersion,
chiselDebug := false,
chiselArgsDebug := Seq("--debug","--vcd"),
chiselArgsC := "--targetDir ../emulator/generated-src --backend c".split(" "),
chiselArgsFpga := "--targetDir ../fpga/generated-src --backend fpga".split(" "),
chiselArgsVlsi := "--targetDir ../vlsi/generated-src --backend v".split(" ")
scalaVersion := buildScalaVersion
)
lazy val chisel = Project("chisel", file("chisel"), settings = buildSettings)
@ -36,31 +25,33 @@ object BuildSettings extends Build {
val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")
def runChisel(args: Seq[String], cp: Classpath, pr: ResolvedProject) = {
val numArgs = 1
require(args.length >= numArgs, "syntax: elaborate <component> [chisel args]")
val projectName = pr.id
val packageName = projectName //TODO: valid convention?
val componentName = args(0)
val classLoader = new java.net.URLClassLoader(cp.map(_.data.toURL).toArray, cp.getClass.getClassLoader)
val chiselMainClass = classLoader.loadClass("Chisel.chiselMain$")
val chiselMainObject = chiselMainClass.getDeclaredFields.head.get(null)
val chiselMain = chiselMainClass.getMethod("run", classOf[Array[String]], classOf[Function0[_]])
val chiselArgs = args.drop(numArgs)
val component = classLoader.loadClass(packageName+"."+componentName)
val generator = () => component.newInstance()
chiselMain.invoke(chiselMainObject, Array(chiselArgs.toArray, generator):_*)
}
val chipSettings = Seq(
elaborateTask <<= inputTask { (argTask: TaskKey[Seq[String]]) =>
(argTask, fullClasspath in Runtime, thisProject, chiselDebug, chiselArgsDebug) map {
(args: Seq[String], cp: Classpath, pr: ResolvedProject, debug: Boolean, debugArgs: Seq[String]) => {
val numArgs = 1
require(args.length >= numArgs, "syntax: elaborate <component> [chisel args]")
val projectName = pr.id
val packageName = projectName //TODO: valid convention?
val componentName = args(0)
val optionalArgs = if(debug) debugArgs else Nil
val classLoader = new java.net.URLClassLoader(cp.map(_.data.toURL).toArray, cp.getClass.getClassLoader)
val chiselMainClass = classLoader.loadClass("Chisel.chiselMain$")
val chiselMainObject = chiselMainClass.getDeclaredFields.head.get(null)
val chiselMain = chiselMainClass.getMethod("run", classOf[Array[String]], classOf[Function0[_]])
val chiselArgs = args.drop(numArgs) ++ optionalArgs
val component = classLoader.loadClass(packageName+"."+componentName)
val generator = () => component.newInstance()
chiselMain.invoke(chiselMainObject, Array(chiselArgs.toArray, generator):_*)
}
(argTask, fullClasspath in Runtime, thisProject) map {
runChisel
}
},
makeTask <<= inputTask { (argTask: TaskKey[Seq[String]]) =>
(argTask) map {
(args: Seq[String]) => {
(argTask, fullClasspath in Runtime, thisProject) map {
(args: Seq[String], cp: Classpath, pr: ResolvedProject) => {
require(args.length >= 2, "syntax: <dir> <target>")
runChisel(args.drop(2), cp, pr)
val makeDir = args(0)
val target = args(1)
val jobs = java.lang.Runtime.getRuntime.availableProcessors