riscv/rocket-chip
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sync up master

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This commit is contained in:
Yunsup Lee 2014-03-20 01:45:23 -07:00
commit 7bbcf920be
6 changed files with 42 additions and 50 deletions
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2
chisel

@ -1 +1 @@
Subproject commit f8c3c094a685c1f5630bd2f61ba0434c2dfbd58f
Subproject commit d151bbeff7bd9917415257482e26760d5fdc1166

2
csrc/emulator.cc
View File

@ -139,7 +139,7 @@ int main(int argc, char** argv)
if (htif->exit_code())
{
fprintf(stderr, "*** FAILED *** (code = %d) after %lld cycles\n", htif->exit_code(), (long long)trace_count);
fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %lld cycles\n", htif->exit_code(), random_seed, (long long)trace_count);
ret = htif->exit_code();
}
else if (trace_count == max_cycles)

82
csrc/vcs_main.cc
View File

@ -8,12 +8,41 @@
#include <sstream>
#include <iterator>
static htif_emulator_t* htif = NULL;
static unsigned htif_bytes;
static mm_t* mm = NULL;
extern "C" {
extern int vcs_main(int argc, char** argv);
static htif_emulator_t* htif;
static unsigned htif_bytes;
static mm_t* mm;
static const char* loadmem;
void htif_fini(vc_handle failure)
{
delete htif;
htif = NULL;
exit(vc_getScalar(failure));
}
int main(int argc, char** argv)
{
bool dramsim = false;
for (int i = 1; i < argc; i++)
{
if (!strcmp(argv[i], "+dramsim"))
dramsim = true;
else if (!strncmp(argv[i], "+loadmem=", 9))
loadmem = argv[i]+9;
}
mm = dramsim ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
htif = new htif_emulator_t(std::vector<std::string>(argv + 1, argv + argc));
vcs_main(argc, argv);
abort(); // should never get here
}
void memory_tick(
vc_handle mem_req_val,
vc_handle mem_req_rdy,
@ -62,55 +91,18 @@ void memory_tick(
);
}
void htif_init
(
vc_handle htif_width,
vc_handle mem_width,
vc_handle argv,
vc_handle loadmem,
vc_handle dramsim
)
void htif_init(vc_handle htif_width, vc_handle mem_width)
{
int mw = vc_4stVectorRef(mem_width)->d;
mm = vc_getScalar(dramsim) ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
assert(mw && (mw & (mw-1)) == 0);
mm->init(MEM_SIZE, mw/8, LINE_SIZE);
if (loadmem)
load_mem(mm->get_data(), loadmem);
vec32* w = vc_4stVectorRef(htif_width);
assert(w->d <= 32 && w->d % 8 == 0); // htif_tick assumes data fits in a vec32
htif_bytes = w->d/8;
char loadmem_str[1024];
vc_VectorToString(loadmem, loadmem_str);
if (*loadmem_str)
load_mem(mm->get_data(), loadmem_str);
char argv_str[1024];
vc_VectorToString(argv, argv_str);
if (!*argv_str)
{
if (*loadmem_str)
strcpy(argv_str, "none");
else
{
fprintf(stderr, "Usage: ./simv [host options] +argv=\"<target program> [target args]\"\n");
exit(-1);
}
}
std::vector<std::string> args;
std::stringstream ss(argv_str);
std::istream_iterator<std::string> begin(ss), end;
std::copy(begin, end, std::back_inserter<std::vector<std::string>>(args));
htif = new htif_emulator_t(args);
}
void htif_fini(vc_handle failure)
{
delete htif;
htif = NULL;
exit(vc_getScalar(failure));
}
void htif_tick

2
hardfloat

@ -1 +1 @@
Subproject commit 2a05ecbb351304464cfedd02890dafb80bfad6d7
Subproject commit 8415eba06ffac9dfa5203bfca9b10afae2316961

2
riscv-tests

@ -1 +1 @@
Subproject commit ea6edc71edb84d9eb9241decd04ee3374a895f0c
Subproject commit 7e1460032cf6f522ce4bc7e8a347c1f08a4476d2

2
rocket

@ -1 +1 @@
Subproject commit ddb2db3f69ffabf9c985f76614603b4b0265c815
Subproject commit 489d3b1cd57bbdcf443247a359214b644c5c1e9f