riscv/rocket-chip
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allocate a primary miss on a prefetch

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This commit is contained in:
Andrew Waterman 2012-02-23 22:37:13 -08:00
parent 2ea309cf80
commit 7b3cce79e3
1 changed files with 2 additions and 1 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -741,10 +741,11 @@ class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
val r_req_store = (r_cpu_req_cmd === M_XWR)
val r_req_flush = (r_cpu_req_cmd === M_FLA)
val r_req_fence = (r_cpu_req_cmd === M_FENCE)
val r_req_prefetch = (r_cpu_req_cmd === M_PFR) || (r_cpu_req_cmd === M_PFW)
val r_req_amo = r_cpu_req_cmd(3).toBool
val r_req_read = r_req_load || r_req_amo
val r_req_write = r_req_store || r_req_amo
val r_req_readwrite = r_req_read || r_req_write
val r_req_readwrite = r_req_read || r_req_write || r_req_prefetch
// replay unit
val replayer = new ReplayUnit()