From 7b3cce79e387583c7f54901a8441a261635449fb Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 23 Feb 2012 22:37:13 -0800 Subject: [PATCH] allocate a primary miss on a prefetch --- rocket/src/main/scala/nbdcache.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 9a8e6d86..96eacb66 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -741,10 +741,11 @@ class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence { val r_req_store = (r_cpu_req_cmd === M_XWR) val r_req_flush = (r_cpu_req_cmd === M_FLA) val r_req_fence = (r_cpu_req_cmd === M_FENCE) + val r_req_prefetch = (r_cpu_req_cmd === M_PFR) || (r_cpu_req_cmd === M_PFW) val r_req_amo = r_cpu_req_cmd(3).toBool val r_req_read = r_req_load || r_req_amo val r_req_write = r_req_store || r_req_amo - val r_req_readwrite = r_req_read || r_req_write + val r_req_readwrite = r_req_read || r_req_write || r_req_prefetch // replay unit val replayer = new ReplayUnit()