reorganize moving non-submodule packages into src/main/scala

Makefrag

@@ -20,9 +20,8 @@ $(FIRRTL_JAR): $(shell find $(base_dir)/firrtl/src/main/scala -iname "*.scala")
 CHISEL_ARGS := --targetDir $(generated_dir)
 
 src_path = src/main/scala
-default_submodules = . junctions uncore hardfloat rocket groundtest coreplex context-dependent-environments
+default_submodules = . hardfloat context-dependent-environments chisel3
-chisel_srcs = $(foreach submodule,$(default_submodules) $(ROCKETCHIP_ADDONS),$(wildcard $(base_dir)/$(submodule)/$(src_path)/*.scala))
+chisel_srcs = $(foreach submodule,$(default_submodules) $(ROCKETCHIP_ADDONS),$(shell find $(base_dir)/$(submodule)/$(src_path) -name "*.scala"))
-chisel_srcs += $(foreach submodule,$(default_submodules) $(ROCKETCHIP_ADDONS),$(wildcard $(base_dir)/$(submodule)/$(src_path)/*/*.scala))
 
 disasm := 2>
 which_disasm := $(shell which spike-dasm 2> /dev/null)

coreplex/build.sbt

@@ -1,10 +0,0 @@
-organization := "edu.berkeley.cs"
-
-version := "1.0"
-
-name := "coreplex"
-
-scalaVersion := "2.11.6"
-
-libraryDependencies ++= (Seq("chisel", "uncore", "junctions", "rocket", "groundtest").map {
-  dep: String => sys.props.get(dep + "Version") map { "edu.berkeley.cs" %% dep % _ }}).flatten

groundtest/.gitignore

@@ -1 +0,0 @@
-target

groundtest/README.md

@@ -1,150 +0,0 @@
-# groundtest
-
-A memory tester circuit for Rocket Chip's memory system. The generator tile
-plugs into the existing SoC generator as what looks like a CPU. However,
-instead of running programs, the tile generates fixed memory requests out to
-the L2. There are both cached and uncached generators. The cached generator
-has an intervening L1 cache, the uncached generator sends TileLink requests
-directly to the L2.
-
-Assertions are set to fail if the wrong data comes back or if a request times
-out waiting for the response.
-
-## Configuring Rocket-Chip with groundtest
-
-The groundtest package defines a GroundTestTile, which extends a
-rocket-chip Tile.  A number of Configs in rocket-chip instantiate
-GroundTestTile(s) in place of other types of Tiles (see
-[TestConfigs.scala](https://github.com/ucb-bar/rocket-chip/blob/master/src/main/scala/TestConfigs.scala)).
-
-Running a ground test can be achieved in rocket-chip as follows
-(assuming the `build.sh` script in the
-`rocket-chip/riscv-tools` directory has already been run).
-
-```
-cd emulator
-make CONFIG=<GroundTestConfigName>
-ln -s ../riscv-tools/riscv-tests/build/isa/rv64ui-p-simple
-./emulator-Top-<GroundTestConfigName> rv64ui-p-simple <other args>
-```
-
-Currently the Configs which include GroundTestTile(s) are:
-
-- MemtestConfig
-- MemtestL2Config
-- BroadcastRegressionTestConfig
-- CacheRegressionTestConfig
-- UnitTestConfig
-- TraceGenConfig
-- ComparatorConfig
-- ComparatorL2Config
-
-The usual Make targets run-asm-tests and run-bmark-tests still work for these configurations, though they don't do much.
-
-## Using TraceGenConfig
-
-The trace generator in groundtest
-([tracegen.scala](https://github.com/ucb-bar/groundtest/blob/master/src/main/scala/tracegen.scala)) has the ability to generate random memory-subsystem traces, i.e. random sequences of memory requests, along with their responses. The idea is that these traces can be validated by an external checker, such as [axe](https://github.com/CTSRD-CHERI/axe).
-
-Putting the generator and the checker together, we can automatically search for invalid traces, i.e. possible bugs in the memory subsystem. This is useful for intensive testing, but also debugging: it is possible to search for simple failing cases.
-
-### Quick Reference
-
-The [tracegen+check.sh](https://github.com/ucb-bar/groundtest/blob/master/scripts/tracegen%2Bcheck.sh) script provides an automated way to run a number of randomized tests. The number of tests, initial seed, and other parameters can be set via environment variables or the command line, see the script for more details. 
-
-Before running the script, first ensure that:
-
-- the file `rocket-chip/riscv-tools/riscv-tests/build/isa/rv64ui-p-simple`
-  exists (this is produced by the `build.sh` script in the
-  `rocket-chip/riscv-tools` directory);
-- `rocket-chip/groundtest/scripts` in your `PATH`;
-- `rocket-chip/emulator` is your current working directory.
-
-Now the script can be run as follows.
-
-```
-> make CONFIG=TraceGenConfig
-> tracegen+check.sh
-Testing against WMO model:
- 
-       0: .......... .......... .......... .......... .......... 
-      50: .......... .......... .......... .......... ..........
-
-OK, passed 100 tests
-LR/SC success rate: 88%
-Load-external rate: 45%
-```
-
-### Running Manually
-
-Suppose we have built the Rocket Chip emulator with the TraceGenConfig
-configuration as above. Running it using the
-[tracegen.py](https://github.com/ucb-bar/groundtest/blob/master/scripts/tracegen.py)
-wrapper script with a few command-line options gives us a random
-trace:
-
-```
-  > tracegen.py ./emulator-Top-TraceGenConfig 1 rv64ui-p-simple
-  1: load-req     0x0000000008 #0 @64
-  1: store-req  5 0x0000100008 #1 @65
-  1: store-req  7 0x0000000010 #2 @66
-  0: store-req  2 0x0000000008 #0 @303
-  0: load-req     0x0000000008 #1 @304
-  0: store-req  6 0x0000100008 #2 @305
-  1: resp       0              #0 @96
-  0: resp       0              #0 @350
-  0: resp       2              #1 @351
-  0: load-req     0x0000000010 #3 @353
-  1: resp       0              #1 @149
-  1: load-req     0x0000000108 #3 @152
-  1: resp       0              #3 @184
-  0: resp       5              #2 @422
-  0: resp       0              #3 @424
-  1: resp       0              #2 @226
-  ...
-```
-
-Main points:
-
-- the second command-line option sets the random seed;
-- the first number on each line of the trace is the core id;
-- \#N denotes a request-id N;
-- @T denotes a time T in clock cycles;
-- hex numbers denote addresses;
-- remaining decimal numbers denote values being loaded or stored;
-- the value written by every store is unique (this simplifies trace checking and reasoning);
-- this trace contains only loads, stores and responses, but the generator (and axe) also support LR/SC pairs, atomics, and fences.
-
-
-We convert these traces to axe format using the
-[toaxe.py](https://github.com/ucb-bar/groundtest/blob/master/scripts/toaxe.py) script.
-
-```
-  > tracegen.py ./emulator-Top-TraceGenConfig 1 rv64ui-p-simple | toaxe.py -
-  # &M[2] == 0x0000000010
-  # &M[0] == 0x0000000008
-  # &M[3] == 0x0000000108
-  # &M[1] == 0x0000100008
-  1: M[0] == 0 @ 64:96
-  1: M[1] := 5 @ 65:
-  1: M[2] := 7 @ 66:
-  0: M[0] := 2 @ 303:
-  0: M[0] == 2 @ 304:351
-  0: M[1] := 6 @ 305:
-  0: M[2] == 0 @ 353:424
-  1: M[3] == 0 @ 152:184
-  ...
-```
-
-Main points:
-
-- lines begining # are comments, showing the addresses being used;
-- after @ are the optional begin and end times of the operation.
-
-Axe traces can be validated using the [axe](https://github.com/CTSRD-CHERI/axe) tool (must be downloaded and installed seperately):
-```
-> tracegen.py ./emulator-Top-TraceGenConfig 1 rv64ui-p-simple | toaxe.py - | axe check WMO -
-OK
-```
-
-Axe reports that this trace is valid according to the WMO model.

groundtest/build.sbt

@@ -1,10 +0,0 @@
-organization := "edu.berkeley.cs"
-
-version := "1.0"
-
-name := "groundtest"
-
-scalaVersion := "2.11.6"
-
-libraryDependencies ++= (Seq("chisel", "uncore", "junctions", "rocket").map {
-  dep: String => sys.props.get(dep + "Version") map { "edu.berkeley.cs" %% dep % _ }}).flatten

junctions/.gitignore

@@ -1,17 +0,0 @@
-*.class
-*.log
-
-# sbt specific
-.cache
-.history
-.lib/
-dist/*
-target/
-lib_managed/
-src_managed/
-project/boot/
-project/plugins/project/
-
-# Scala-IDE specific
-.scala_dependencies
-.worksheet

junctions/LICENSE

@@ -1,28 +0,0 @@
-Copyright (c) 2015, The Regents of the University of California (Regents)
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright notice,
-  this list of conditions and the following disclaimer in the documentation
-  and/or other materials provided with the distribution.
-
-* Neither the name of junctions nor the names of its
-  contributors may be used to endorse or promote products derived from
-  this software without specific prior written permission.
-
-IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
-SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
-OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
-BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
-HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
-MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
-

junctions/README.md

@@ -1,6 +0,0 @@
-# junctions
-A repository for peripheral components and IO devices associated with the RocketChip project.
-
-To uses these modules, include this repo as a git submodule within the your chip repository and add it as Project in your chip's build.scala. These components are only dependent on Chisel, i.e.
-
-    lazy val junctions = project.dependsOn(chisel)

junctions/build.sbt

@@ -1,19 +0,0 @@
-organization := "edu.berkeley.cs"
-
-version := "1.0"
-
-name := "junctions"
-
-scalaVersion := "2.11.6"
-
-// Provide a managed dependency on chisel if -DchiselVersion="" is supplied on the command line.
-libraryDependencies ++= (Seq("chisel","cde").map {
-  dep: String => sys.props.get(dep + "Version") map { "edu.berkeley.cs" %% dep % _ }}).flatten
-
-site.settings
-
-site.includeScaladoc()
-
-ghpages.settings
-
-git.remoteRepo := "git@github.com:ucb-bar/junctions.git"

junctions/project/plugins.sbt

@@ -1,5 +0,0 @@
-resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven"
-
-addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.5.3")
-
-addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "0.8.1")

project/build.scala

@@ -19,12 +19,7 @@ object BuildSettings extends Build {
   lazy val chisel = project in file("chisel3")
   lazy val cde        = project in file("context-dependent-environments")
   lazy val hardfloat  = project.dependsOn(chisel)
-  lazy val junctions  = project.dependsOn(chisel, cde)
+  lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(chisel, cde, hardfloat)
-  lazy val uncore     = project.dependsOn(junctions)
-  lazy val rocket     = project.dependsOn(hardfloat, uncore)
-  lazy val groundtest = project.dependsOn(rocket)
-  lazy val coreplex   = project.dependsOn(groundtest)
-  lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(coreplex)
 
   lazy val addons = settingKey[Seq[String]]("list of addons used for this build")
   lazy val make = inputKey[Unit]("trigger backend-specific makefile command")

rocket/.gitignore

@@ -1 +0,0 @@
-target

rocket/LICENSE

@@ -1,24 +0,0 @@
-Copyright (c) 2011-2014, The Regents of the University of California
-(Regents).  All Rights Reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-3. Neither the name of the Regents nor the
-   names of its contributors may be used to endorse or promote products
-   derived from this software without specific prior written permission.
-
-IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
-SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
-OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
-BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
-HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
-MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.

rocket/README.md

@@ -1,29 +0,0 @@
-Rocket Core
-===========
-
-Rocket is a 6-stage single-issue in-order pipeline that executes the 64-bit
-scalar RISC-V ISA.  Rocket implements an MMU that supports page-based virtual
-memory and is able to boot modern operating systems such as Linux.  Rocket
-also has an optional IEEE 754-2008-compliant FPU, which implements both
-single- and double-precision floating-point operations, including fused
-multiply-add.
-
-This repository is not intended to be a self-running repository. To
-instantiate a Rocket core, please use the Rocket chip generator found in the
-rocket-chip git repository.
-
-The following table compares a 32-bit ARM Cortex-A5 core to a 64-bit RISC-V
-Rocket core built in the same TSMC process (40GPLUS). Fourth column is the
-ratio of RISC-V Rocket to ARM Cortex-A5. Both use single-instruction-issue,
-in-order pipelines, yet the RISC-V core is faster, smaller, and uses less
-power.
-
-ISA/Implementation | ARM Cortex-A5 | RISC-V Rocket | R/A
---- | --- | --- | ---
-ISA Register Width | 32 bits | 64 bits | 2
-Frequency | >1 GHz | >1 GHz | 1
-Dhrystone Performance | 1.57 DMIPS/MHz | 1.72 DMIPS/MHz | 1.1
-Area excluding caches | 0.27 mm<sup>2</sup> | 0.14 mm<sup>2</sup> | 0.5
-Area with 16KB caches | 0.53 mm<sup>2</sup> | 0.39 mm<sup>2</sup> | 0.7
-Area Efficiency | 2.96 DMIPS/MHz/mm<sup>2</sup> | 4.41 DMIPS/MHz/mm<sup>2</sup> | 1.5
-Dynamic Power | <0.08 mW/MHz | 0.034 mW/MHz | >= 0.4

rocket/build.sbt

@@ -1,10 +0,0 @@
-organization := "edu.berkeley.cs"
-
-version := "1.2"
-
-name := "rocket"
-
-scalaVersion := "2.11.6"
-
-libraryDependencies ++= (Seq("chisel", "hardfloat", "uncore", "junctions", "cde").map {
-  dep: String => sys.props.get(dep + "Version") map { "edu.berkeley.cs" %% dep % _ }}).flatten