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debug: Properly consider 'transfer' bit

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Megan Wachs 2017-04-11 15:50:32 -07:00 committed by Yunsup Lee
parent 2dc4be6294
commit 79477fbea6
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/uncore/devices/debug/Debug.scala
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@ -834,7 +834,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
nop.imm := 0.U
when (goAbstract) {
abstractGeneratedMem(0) := Mux(/*TODO: accessRegisterCommandReg.transfer*/true.B,
abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer,
Mux(accessRegisterCommandReg.write,
// To write a register, we need to do LW.
abstractGeneratedI.asUInt(),
@ -915,7 +915,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
val commandRegIsUnsupported = Wire(init = true.B)
val commandRegBadHaltResume = Wire(init = false.B)
when (commandRegIsAccessRegister) {
when (commandRegIsAccessRegister && accessRegisterCommandReg.transfer) {
when ((accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U)){
commandRegIsUnsupported := false.B
commandRegBadHaltResume := ~hartHalted