From 79477fbea63625e2c5c289733f253b162ac2924e Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 11 Apr 2017 15:50:32 -0700 Subject: [PATCH] debug: Properly consider 'transfer' bit --- src/main/scala/uncore/devices/debug/Debug.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/devices/debug/Debug.scala b/src/main/scala/uncore/devices/debug/Debug.scala index 841fcc6c..b3eb2348 100644 --- a/src/main/scala/uncore/devices/debug/Debug.scala +++ b/src/main/scala/uncore/devices/debug/Debug.scala @@ -834,7 +834,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p: nop.imm := 0.U when (goAbstract) { - abstractGeneratedMem(0) := Mux(/*TODO: accessRegisterCommandReg.transfer*/true.B, + abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, // To write a register, we need to do LW. abstractGeneratedI.asUInt(), @@ -915,7 +915,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p: val commandRegIsUnsupported = Wire(init = true.B) val commandRegBadHaltResume = Wire(init = false.B) - when (commandRegIsAccessRegister) { + when (commandRegIsAccessRegister && accessRegisterCommandReg.transfer) { when ((accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U)){ commandRegIsUnsupported := false.B commandRegBadHaltResume := ~hartHalted