riscv/rocket-chip
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Update firrtl and remove firrtl hack in plic

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This commit is contained in:
Andrew Waterman
2016-08-02 14:37:59 -07:00
parent f04aefc95c
commit 791a27748b
2 changed files with 2 additions and 2 deletions
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2
firrtl

Submodule firrtl updated: 81f631bc87...3e2ff71db6

2
uncore/src/main/scala/devices/Plic.scala
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@ -112,7 +112,7 @@ class PLIC(val cfg: PLICConfig)(implicit val p: Parameters) extends Module
if (cfg.nHarts == 1) UInt(0) if (cfg.nHarts == 1) UInt(0)
else (addr - cfg.hartBase)(log2Up(cfg.hartOffset(cfg.nHarts))-1,log2Up(cfg.hartOffset(1))) else (addr - cfg.hartBase)(log2Up(cfg.hartOffset(cfg.nHarts))-1,log2Up(cfg.hartOffset(1)))
val hart = Wire(init = claimant) val hart = Wire(init = claimant)
val myMaxDev = maxDevs(claimant) + UInt(0) // XXX FIRRTL bug w/o the + UInt(0) val myMaxDev = maxDevs(claimant)
val myEnables = enables(hart) val myEnables = enables(hart)
val rdata = Wire(init = UInt(0, tlDataBits)) val rdata = Wire(init = UInt(0, tlDataBits))
val masked_wdata = (acq.bits.data & acq.bits.full_wmask()) | (rdata & ~acq.bits.full_wmask()) val masked_wdata = (acq.bits.data & acq.bits.full_wmask()) | (rdata & ~acq.bits.full_wmask())