From 791a27748b7852407de6b2112b9fd1c21049402e Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 2 Aug 2016 14:37:59 -0700 Subject: [PATCH] Update firrtl and remove firrtl hack in plic --- firrtl | 2 +- uncore/src/main/scala/devices/Plic.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/firrtl b/firrtl index 81f631bc..3e2ff71d 160000 --- a/firrtl +++ b/firrtl @@ -1 +1 @@ -Subproject commit 81f631bc87aa22fff8569e96ae5c4e429df9e1d4 +Subproject commit 3e2ff71db633315455a72b00fc277dda18aca317 diff --git a/uncore/src/main/scala/devices/Plic.scala b/uncore/src/main/scala/devices/Plic.scala index 193cf898..2108fadf 100644 --- a/uncore/src/main/scala/devices/Plic.scala +++ b/uncore/src/main/scala/devices/Plic.scala @@ -112,7 +112,7 @@ class PLIC(val cfg: PLICConfig)(implicit val p: Parameters) extends Module if (cfg.nHarts == 1) UInt(0) else (addr - cfg.hartBase)(log2Up(cfg.hartOffset(cfg.nHarts))-1,log2Up(cfg.hartOffset(1))) val hart = Wire(init = claimant) - val myMaxDev = maxDevs(claimant) + UInt(0) // XXX FIRRTL bug w/o the + UInt(0) + val myMaxDev = maxDevs(claimant) val myEnables = enables(hart) val rdata = Wire(init = UInt(0, tlDataBits)) val masked_wdata = (acq.bits.data & acq.bits.full_wmask()) | (rdata & ~acq.bits.full_wmask())