riscv/rocket-chip
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Trace tval field should be zero when not taking exceptions

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This commit is contained in:
Andrew Waterman 2017-09-27 12:51:10 -07:00
parent 583adeee88
commit 78f3877e02
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/CSR.scala
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@ -520,7 +520,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
assert(!reg_singleStepped || io.retire === UInt(0)) assert(!reg_singleStepped || io.retire === UInt(0))
val epc = ~(~io.pc | (coreInstBytes-1)) val epc = ~(~io.pc | (coreInstBytes-1))
val write_badaddr = cause isOneOf (Causes.illegal_instruction, Causes.breakpoint, val write_badaddr = exception && cause.isOneOf(Causes.illegal_instruction, Causes.breakpoint,
Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_load, Causes.misaligned_store,
Causes.load_access, Causes.store_access, Causes.fetch_access, Causes.load_access, Causes.store_access, Causes.fetch_access,
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault) Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)