From 78f3877e02fb5f61e4607846fc9f5fc73829915d Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 27 Sep 2017 12:51:10 -0700 Subject: [PATCH] Trace tval field should be zero when not taking exceptions --- src/main/scala/rocket/CSR.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 13605307..c3a05712 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -520,7 +520,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param assert(!reg_singleStepped || io.retire === UInt(0)) val epc = ~(~io.pc | (coreInstBytes-1)) - val write_badaddr = cause isOneOf (Causes.illegal_instruction, Causes.breakpoint, + val write_badaddr = exception && cause.isOneOf(Causes.illegal_instruction, Causes.breakpoint, Causes.misaligned_load, Causes.misaligned_store, Causes.load_access, Causes.store_access, Causes.fetch_access, Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)