riscv/rocket-chip
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refactor fpga top/config

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This commit is contained in:
Henry Cook 2014-08-28 13:07:54 -07:00
parent bf356b9cb4
commit 78ab83d224
3 changed files with 34 additions and 5 deletions
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35
src/main/scala/PublicConfigs.scala
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@ -5,9 +5,6 @@ import uncore._
import rocket._ import rocket._
import rocket.Util._ import rocket.Util._
class DefaultVLSIConfig extends DefaultConfig
class DefaultFPGAConfig extends DefaultConfig
class DefaultCPPConfig extends DefaultConfig
class DefaultConfig extends ChiselConfig { class DefaultConfig extends ChiselConfig {
val top:World.TopDefs = { val top:World.TopDefs = {
(pname,site,here) => pname match { (pname,site,here) => pname match {
@ -145,4 +142,36 @@ class DefaultConfig extends ChiselConfig {
case "L1D_WAYS" => 4 case "L1D_WAYS" => 4
} }
} }
class DefaultVLSIConfig extends DefaultConfig
class DefaultCPPConfig extends DefaultConfig
class FPGAConfig(default: ChiselConfig) extends ChiselConfig {
val top:World.TopDefs = {
(pname,site,here) => pname match {
case NSets => site(CacheName) match {
case "L1I" => 64
case "L1D" => Knob("L1D_SETS")
}
case NWays => site(CacheName) match {
case "L1I" => 1
case "L1D" => Knob("L1D_WAYS")
}
case FastMulDiv => false
case NITLBEntries => 4
case NBTBEntries => 8
case NDTLBEntries => 4
case _ => default.top(pname,site,here)
}
}
override val knobVal:Any=>Any = {
case "NTILES" => 1
case "NBANKS" => 1
case "L2_REL_XACTS" => 1
case "L2_ACQ_XACTS" => 7
case "L1D_MSHRS" => 2
case "L1D_SETS" => 64
case "L1D_WAYS" => 1
}
}
class DefaultFPGAConfig extends FPGAConfig(new DefaultConfig)

2
src/main/scala/RocketChip.scala
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@ -58,7 +58,7 @@ class OuterMemorySystem extends Module with TopLevelParameters {
// Create a SerDes for backup memory port // Create a SerDes for backup memory port
if(params(UseBackupMemoryPort)) { if(params(UseBackupMemoryPort)) {
VLSIUtils.doOuterMemorySystemSerdes(llc.io.mem, io.mem, io.mem_backup, VLSIUtils.doOuterMemorySystemSerdes(llc.io.mem, io.mem, io.mem_backup,
io.mem_backup_en, params(HTIFWidth)) io.mem_backup_en, htifW)
} else { } else {
io.mem <> llc.io.mem io.mem <> llc.io.mem
} }

2
src/main/scala/fpga.scala
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@ -64,7 +64,7 @@ class Slave extends AXISlave
// write cr1 -> mem.resp (nonblocking) // write cr1 -> mem.resp (nonblocking)
val in_count = Reg(init=UInt(0, log2Up(memw/dw))) val in_count = Reg(init=UInt(0, log2Up(memw/dw)))
val rf_count = Reg(init=UInt(0, log2Up(params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8/memw))) val rf_count = Reg(init=UInt(0, log2Up(params(CacheBlockBytes)*8/memw)))
require(memw % dw == 0 && isPow2(memw/dw)) require(memw % dw == 0 && isPow2(memw/dw))
val in_reg = Reg(top.io.mem.resp.bits.data) val in_reg = Reg(top.io.mem.resp.bits.data)
top.io.mem.resp.bits.data := Cat(io.in.bits, in_reg(in_reg.getWidth-1,dw)) top.io.mem.resp.bits.data := Cat(io.in.bits, in_reg(in_reg.getWidth-1,dw))