From 78ab83d224130be39684dda8237cda403837b410 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Thu, 28 Aug 2014 13:07:54 -0700
Subject: [PATCH] refactor fpga top/config

---
 src/main/scala/PublicConfigs.scala | 35 +++++++++++++++++++++++++++---
 src/main/scala/RocketChip.scala    |  2 +-
 src/main/scala/fpga.scala          |  2 +-
 3 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/PublicConfigs.scala b/src/main/scala/PublicConfigs.scala
index 8fd57a18..e074b020 100644
--- a/src/main/scala/PublicConfigs.scala
+++ b/src/main/scala/PublicConfigs.scala
@@ -5,9 +5,6 @@ import uncore._
 import rocket._
 import rocket.Util._
 
-class DefaultVLSIConfig extends DefaultConfig
-class DefaultFPGAConfig extends DefaultConfig
-class DefaultCPPConfig extends DefaultConfig
 class DefaultConfig extends ChiselConfig {
   val top:World.TopDefs = {
     (pname,site,here) => pname match {
@@ -145,4 +142,36 @@ class DefaultConfig extends ChiselConfig {
     case "L1D_WAYS" => 4
   }
 }
+class DefaultVLSIConfig extends DefaultConfig
+class DefaultCPPConfig extends DefaultConfig
 
+class FPGAConfig(default: ChiselConfig) extends ChiselConfig {
+  val top:World.TopDefs = {
+    (pname,site,here) => pname match {
+      case NSets => site(CacheName) match {
+        case "L1I" => 64
+        case "L1D" => Knob("L1D_SETS")
+      }
+      case NWays => site(CacheName) match {
+        case "L1I" => 1
+        case "L1D" => Knob("L1D_WAYS")
+      }
+      case FastMulDiv => false
+      case NITLBEntries => 4
+      case NBTBEntries => 8
+      case NDTLBEntries => 4
+      case _ => default.top(pname,site,here)
+    }
+  }
+  override val knobVal:Any=>Any = {
+    case "NTILES" => 1
+    case "NBANKS" => 1
+    case "L2_REL_XACTS" => 1
+    case "L2_ACQ_XACTS" => 7
+    case "L1D_MSHRS" => 2
+    case "L1D_SETS" => 64
+    case "L1D_WAYS" => 1
+  }
+}
+
+class DefaultFPGAConfig extends FPGAConfig(new DefaultConfig)
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 3a393126..acb7d0a9 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -58,7 +58,7 @@ class OuterMemorySystem extends Module with TopLevelParameters {
   // Create a SerDes for backup memory port
   if(params(UseBackupMemoryPort)) {
     VLSIUtils.doOuterMemorySystemSerdes(llc.io.mem, io.mem, io.mem_backup,
-                                        io.mem_backup_en, params(HTIFWidth))
+                                        io.mem_backup_en, htifW)
   } else {
     io.mem <> llc.io.mem 
   }
diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala
index 95290b46..5900fea8 100644
--- a/src/main/scala/fpga.scala
+++ b/src/main/scala/fpga.scala
@@ -64,7 +64,7 @@ class Slave extends AXISlave
 
   // write cr1 -> mem.resp (nonblocking)
   val in_count = Reg(init=UInt(0, log2Up(memw/dw)))
-  val rf_count = Reg(init=UInt(0, log2Up(params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8/memw)))
+  val rf_count = Reg(init=UInt(0, log2Up(params(CacheBlockBytes)*8/memw)))
   require(memw % dw == 0 && isPow2(memw/dw))
   val in_reg = Reg(top.io.mem.resp.bits.data)
   top.io.mem.resp.bits.data := Cat(io.in.bits, in_reg(in_reg.getWidth-1,dw))