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ahb: parameterize poci

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This commit is contained in:
Wesley W. Terpstra 2016-05-18 16:10:57 -07:00
parent 93447eb274
commit 7896c4157e
2 changed files with 7 additions and 13 deletions
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2
junctions/src/main/scala/package.scala
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@ -1 +1 @@
package object junctions extends HastiConstants with PociConstants package object junctions extends HastiConstants

18
junctions/src/main/scala/poci.scala
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@ -3,20 +3,14 @@ package junctions
import Chisel._ import Chisel._
import cde.{Parameters, Field} import cde.{Parameters, Field}
abstract trait PociConstants class PociIO(implicit p: Parameters) extends HastiBundle()(p)
{ {
val SZ_PADDR = 32 val paddr = UInt(OUTPUT, hastiAddrBits)
val SZ_PDATA = 32
}
class PociIO extends Bundle
{
val paddr = UInt(OUTPUT, SZ_PADDR)
val pwrite = Bool(OUTPUT) val pwrite = Bool(OUTPUT)
val psel = Bool(OUTPUT) val psel = Bool(OUTPUT)
val penable = Bool(OUTPUT) val penable = Bool(OUTPUT)
val pwdata = UInt(OUTPUT, SZ_PDATA) val pwdata = UInt(OUTPUT, hastiDataBits)
val prdata = UInt(INPUT, SZ_PDATA) val prdata = UInt(INPUT, hastiDataBits)
val pready = Bool(INPUT) val pready = Bool(INPUT)
val pslverr = Bool(INPUT) val pslverr = Bool(INPUT)
} }
@ -45,7 +39,7 @@ class HastiToPociBridge(implicit p: Parameters) extends HastiModule()(p) {
} }
} }
val haddr_reg = Reg(UInt(width = SZ_PADDR)) val haddr_reg = Reg(UInt(width = hastiAddrBits))
val hwrite_reg = Reg(UInt(width = 1)) val hwrite_reg = Reg(UInt(width = 1))
when (transfer) { when (transfer) {
haddr_reg := io.in.haddr haddr_reg := io.in.haddr
@ -62,7 +56,7 @@ class HastiToPociBridge(implicit p: Parameters) extends HastiModule()(p) {
io.in.hresp := io.out.pslverr io.in.hresp := io.out.pslverr
} }
class PociBus(amap: Seq[UInt=>Bool]) extends Module class PociBus(amap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModule()(p)
{ {
val io = new Bundle { val io = new Bundle {
val master = new PociIO().flip val master = new PociIO().flip