From 7896c4157e859cb23e886fb66e45c0e795ac4cb8 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 18 May 2016 16:10:57 -0700
Subject: [PATCH] ahb: parameterize poci

---
 junctions/src/main/scala/package.scala |  2 +-
 junctions/src/main/scala/poci.scala    | 18 ++++++------------
 2 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/junctions/src/main/scala/package.scala b/junctions/src/main/scala/package.scala
index 3181064e..317b7109 100644
--- a/junctions/src/main/scala/package.scala
+++ b/junctions/src/main/scala/package.scala
@@ -1 +1 @@
-package object junctions extends HastiConstants with PociConstants
+package object junctions extends HastiConstants
diff --git a/junctions/src/main/scala/poci.scala b/junctions/src/main/scala/poci.scala
index 01993fee..976fd304 100644
--- a/junctions/src/main/scala/poci.scala
+++ b/junctions/src/main/scala/poci.scala
@@ -3,20 +3,14 @@ package junctions
 import Chisel._
 import cde.{Parameters, Field}
 
-abstract trait PociConstants
+class PociIO(implicit p: Parameters) extends HastiBundle()(p)
 {
-  val SZ_PADDR = 32
-  val SZ_PDATA = 32
-}
-
-class PociIO extends Bundle
-{
-  val paddr = UInt(OUTPUT, SZ_PADDR)
+  val paddr = UInt(OUTPUT, hastiAddrBits)
   val pwrite = Bool(OUTPUT)
   val psel = Bool(OUTPUT)
   val penable = Bool(OUTPUT)
-  val pwdata = UInt(OUTPUT, SZ_PDATA)
-  val prdata = UInt(INPUT, SZ_PDATA)
+  val pwdata = UInt(OUTPUT, hastiDataBits)
+  val prdata = UInt(INPUT, hastiDataBits)
   val pready = Bool(INPUT)
   val pslverr = Bool(INPUT)
 }
@@ -45,7 +39,7 @@ class HastiToPociBridge(implicit p: Parameters) extends HastiModule()(p) {
     }
   }
 
-  val haddr_reg = Reg(UInt(width = SZ_PADDR))
+  val haddr_reg = Reg(UInt(width = hastiAddrBits))
   val hwrite_reg = Reg(UInt(width = 1))
   when (transfer) {
     haddr_reg  := io.in.haddr
@@ -62,7 +56,7 @@ class HastiToPociBridge(implicit p: Parameters) extends HastiModule()(p) {
   io.in.hresp := io.out.pslverr
 }
 
-class PociBus(amap: Seq[UInt=>Bool]) extends Module
+class PociBus(amap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModule()(p)
 {
   val io = new Bundle {
     val master = new PociIO().flip