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subsystem: add TLIdentity.gen and make wrappers more flexible

This commit is contained in:
Henry Cook 2018-02-21 18:22:06 -08:00
parent eaa908d44f
commit 78883d13e8
5 changed files with 54 additions and 28 deletions

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@ -56,17 +56,12 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWr
} }
} }
def toDRAMController( def toDRAMController[D,U,E,B <: Data](
name: Option[String] = None, name: Option[String] = None,
buffer: BufferParams = BufferParams.none) buffer: BufferParams = BufferParams.none)
(gen: => TLInwardNode) { (gen: => NodeHandle[
to("memory_controller" named name) { gen := bufferTo(buffer) } TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
} D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
def toDRAMControllerPort[D,U,E,B <: Data](
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {
to("memory_controller" named name) { gen := bufferTo(buffer) } to("memory_controller" named name) { gen := bufferTo(buffer) }
} }

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@ -33,34 +33,42 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
private def fixedWidthTo(buffer: BufferParams): TLOutwardNode = private def fixedWidthTo(buffer: BufferParams): TLOutwardNode =
TLWidthWidget(params.beatBytes) :*= bufferTo(buffer) TLWidthWidget(params.beatBytes) :*= bufferTo(buffer)
def toSlave( def toSlave[D,U,E,B <: Data](
name: Option[String] = None, name: Option[String] = None,
buffer: BufferParams = BufferParams.none) buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = { (gen: => NodeHandle[
TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
to("slave" named name) { gen :*= bufferTo(buffer) } to("slave" named name) { gen :*= bufferTo(buffer) }
} }
def toVariableWidthSlave( def toVariableWidthSlave[D,U,E,B <: Data](
name: Option[String] = None, name: Option[String] = None,
buffer: BufferParams = BufferParams.none) buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = { (gen: => NodeHandle[
TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
to("slave" named name) { to("slave" named name) {
gen :*= fragmentTo(params.beatBytes, params.blockBytes, buffer) gen :*= fragmentTo(params.beatBytes, params.blockBytes, buffer)
} }
} }
def toFixedWidthSlave( def toFixedWidthSlave[D,U,E,B <: Data](
name: Option[String] = None, name: Option[String] = None,
buffer: BufferParams = BufferParams.none) buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = { (gen: => NodeHandle[
TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
to("slave" named name) { gen :*= fixedWidthTo(buffer) } to("slave" named name) { gen :*= fixedWidthTo(buffer) }
} }
def toFixedWidthSingleBeatSlave( def toFixedWidthSingleBeatSlave[D,U,E,B <: Data](
widthBytes: Int, widthBytes: Int,
name: Option[String] = None, name: Option[String] = None,
buffer: BufferParams = BufferParams.none) buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = { (gen: => NodeHandle[
TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
to("slave" named name) { to("slave" named name) {
gen :*= TLFragmenter(widthBytes, params.blockBytes) :*= fixedWidthTo(buffer) gen :*= TLFragmenter(widthBytes, params.blockBytes) :*= fixedWidthTo(buffer)
} }
@ -76,6 +84,14 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
} }
} }
def toFixedWidthPort[D,U,E,B <: Data](
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {
to("port" named name) { gen := fixedWidthTo(buffer) }
}
def fromSystemBus( def fromSystemBus(
arithmetic: Boolean = true, arithmetic: Boolean = true,
buffer: BufferParams = BufferParams.default) buffer: BufferParams = BufferParams.default)

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@ -52,7 +52,7 @@ trait HasMasterAXI4MemPort { this: BaseSubsystem =>
}) })
memBuses.map { m => memBuses.map { m =>
mem_axi4 := m.toDRAMControllerPort(Some(portName)) { mem_axi4 := m.toDRAMController(Some(portName)) {
(AXI4UserYanker() := AXI4IdIndexer(params.idBits) := TLToAXI4()) (AXI4UserYanker() := AXI4IdIndexer(params.idBits) := TLToAXI4())
} }
} }

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@ -47,7 +47,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def toSplitSlave(name: Option[String] = None) def toSplitSlave(name: Option[String] = None)
(gen: => TLNode): TLOutwardNode = { (gen: => TLNode): TLOutwardNode = {
to("slave" named name) { gen :*= master_splitter.node } to("slave" named name) { gen :=* master_splitter.node }
} }
def toFixedWidthSlave( def toFixedWidthSlave(
@ -66,12 +66,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
} }
} }
def fromCoherentChip(gen: => TLNode): TLInwardNode = {
from("CoherentChip") { inwardNode :=* gen }
}
def fromFrontBus(gen: => TLNode): TLInwardNode = { def fromFrontBus(gen: => TLNode): TLInwardNode = {
from("FrontBus") { master_splitter.node :=* gen } from("front_bus") { master_splitter.node :=* gen }
} }
def fromTile( def fromTile(
@ -104,15 +100,27 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
} }
} }
def fromCoherentMaster(
name: Option[String] = None,
buffers: Int = 0)
(gen: => TLNode): TLInwardNode = {
from("coherent_master" named name) {
(inwardNode
:=* TLFIFOFixer(TLFIFOFixer.all)
:=* TLBuffer.chain(buffers).reduce(_ :=* _)
:=* gen)
}
}
def fromMaster( def fromMaster(
name: Option[String] = None, name: Option[String] = None,
buffers: Int = 0) buffers: Int = 0)
(gen: => TLNode): TLInwardNode = { (gen: => TLNode): TLInwardNode = {
from("master" named name) { from("master" named name) {
(List( (master_splitter.node
master_splitter.node, :=* TLFIFOFixer(TLFIFOFixer.all)
TLFIFOFixer(TLFIFOFixer.all)) ++ :=* TLBuffer.chain(buffers).reduce(_ :=* _)
TLBuffer.chain(buffers)).reduce(_ :=* _) :=* gen :=* gen)
} }
} }
} }

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@ -54,3 +54,10 @@ trait HasTLXbarPhy { this: TLBusWrapper =>
protected def inwardNode: TLInwardNode = xbar.node protected def inwardNode: TLInwardNode = xbar.node
protected def outwardNode: TLOutwardNode = xbar.node protected def outwardNode: TLOutwardNode = xbar.node
} }
object TLIdentity {
def gen: TLNode = {
val passthru = TLIdentityNode()
passthru
}
}