subsystem: add TLIdentity.gen and make wrappers more flexible

src/main/scala/subsystem/MemoryBus.scala

@@ -56,17 +56,12 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWr
     }
   }
 
-  def toDRAMController(
+  def toDRAMController[D,U,E,B <: Data](
         name: Option[String] = None,
         buffer: BufferParams = BufferParams.none)
-      (gen: => TLInwardNode) {
+      (gen: => NodeHandle[
-    to("memory_controller" named name) { gen := bufferTo(buffer) }
+                TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
-  }
+                D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
-
-  def toDRAMControllerPort[D,U,E,B <: Data](
-        name: Option[String] = None,
-        buffer: BufferParams = BufferParams.none)
-      (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {
     to("memory_controller" named name) { gen := bufferTo(buffer) }
   }
 

src/main/scala/subsystem/PeripheryBus.scala

@@ -33,34 +33,42 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
   private def fixedWidthTo(buffer: BufferParams): TLOutwardNode =
     TLWidthWidget(params.beatBytes) :*= bufferTo(buffer)
 
-  def toSlave(
+  def toSlave[D,U,E,B <: Data](
         name: Option[String] = None,
         buffer: BufferParams = BufferParams.none)
-      (gen: => TLNode): TLOutwardNode = {
+      (gen: => NodeHandle[
+                TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
+                D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
     to("slave" named name) { gen :*= bufferTo(buffer) }
   }
 
-  def toVariableWidthSlave(
+  def toVariableWidthSlave[D,U,E,B <: Data](
         name: Option[String] = None,
         buffer: BufferParams = BufferParams.none)
-      (gen: => TLNode): TLOutwardNode = {
+      (gen: => NodeHandle[
+                TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
+                D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
     to("slave" named name) {
       gen :*= fragmentTo(params.beatBytes, params.blockBytes, buffer)
     }
   }
 
-  def toFixedWidthSlave(
+  def toFixedWidthSlave[D,U,E,B <: Data](
         name: Option[String] = None,
         buffer: BufferParams = BufferParams.none)
-      (gen: => TLNode): TLOutwardNode = {
+      (gen: => NodeHandle[
+                TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
+                D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
     to("slave" named name) { gen :*= fixedWidthTo(buffer) }
   }
 
-  def toFixedWidthSingleBeatSlave(
+  def toFixedWidthSingleBeatSlave[D,U,E,B <: Data](
         widthBytes: Int,
         name: Option[String] = None,
         buffer: BufferParams = BufferParams.none)
-      (gen: => TLNode): TLOutwardNode = {
+      (gen: => NodeHandle[
+                TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
+                D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
     to("slave" named name) {
       gen :*= TLFragmenter(widthBytes, params.blockBytes) :*= fixedWidthTo(buffer)
     }
@@ -76,6 +84,14 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
     }
   }
 
+  def toFixedWidthPort[D,U,E,B <: Data](
+        name: Option[String] = None,
+        buffer: BufferParams = BufferParams.none)
+      (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {
+    to("port" named name) { gen := fixedWidthTo(buffer) }
+  }
+
+
   def fromSystemBus(
         arithmetic: Boolean = true,
         buffer: BufferParams = BufferParams.default)

src/main/scala/subsystem/Ports.scala

@@ -52,7 +52,7 @@ trait HasMasterAXI4MemPort { this: BaseSubsystem =>
   })
 
   memBuses.map { m =>
-    mem_axi4 := m.toDRAMControllerPort(Some(portName)) {
+    mem_axi4 := m.toDRAMController(Some(portName)) {
       (AXI4UserYanker() := AXI4IdIndexer(params.idBits) := TLToAXI4())
     }
   }

src/main/scala/subsystem/SystemBus.scala

@@ -47,7 +47,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
  
   def toSplitSlave(name: Option[String] = None)
                   (gen: => TLNode): TLOutwardNode = {
-    to("slave" named name) { gen :*= master_splitter.node }
+    to("slave" named name) { gen :=* master_splitter.node }
   }
 
   def toFixedWidthSlave(
@@ -66,12 +66,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
     }
   }
 
-  def fromCoherentChip(gen: => TLNode): TLInwardNode = {
-    from("CoherentChip") { inwardNode :=* gen }
-  }
-
   def fromFrontBus(gen: => TLNode): TLInwardNode = {
-    from("FrontBus") { master_splitter.node :=* gen }
+    from("front_bus") { master_splitter.node :=* gen }
   }
 
   def fromTile(
@@ -104,15 +100,27 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
     }
   }
 
+  def fromCoherentMaster(
+        name: Option[String] = None,
+        buffers: Int = 0)
+      (gen: => TLNode): TLInwardNode = {
+    from("coherent_master" named name) {
+      (inwardNode
+        :=* TLFIFOFixer(TLFIFOFixer.all)
+        :=* TLBuffer.chain(buffers).reduce(_ :=* _)
+        :=* gen)
+    }
+  }
+
   def fromMaster(
         name: Option[String] = None,
         buffers: Int = 0)
       (gen: => TLNode): TLInwardNode = {
     from("master" named name) {
-      (List(
+      (master_splitter.node
-        master_splitter.node,
+        :=* TLFIFOFixer(TLFIFOFixer.all)
-        TLFIFOFixer(TLFIFOFixer.all)) ++
+        :=* TLBuffer.chain(buffers).reduce(_ :=* _)
-        TLBuffer.chain(buffers)).reduce(_ :=* _) :=* gen
+        :=* gen)
     }
   }
 }

src/main/scala/tilelink/BusWrapper.scala

@@ -54,3 +54,10 @@ trait HasTLXbarPhy { this: TLBusWrapper =>
   protected def inwardNode: TLInwardNode = xbar.node
   protected def outwardNode: TLOutwardNode = xbar.node
 }
+
+object TLIdentity {
+  def gen: TLNode = {
+    val passthru = TLIdentityNode()
+    passthru
+  }
+}