riscv/rocket-chip
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subsystem: add TLIdentity.gen and make wrappers more flexible

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This commit is contained in:
Henry Cook
2018-02-21 18:22:06 -08:00
parent eaa908d44f
commit 78883d13e8
5 changed files with 54 additions and 28 deletions
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28
src/main/scala/subsystem/SystemBus.scala
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@ -47,7 +47,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def toSplitSlave(name: Option[String] = None)
(gen: => TLNode): TLOutwardNode = {
to("slave" named name) { gen :*= master_splitter.node }
to("slave" named name) { gen :=* master_splitter.node }
}
def toFixedWidthSlave(
@ -66,12 +66,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
}
}
def fromCoherentChip(gen: => TLNode): TLInwardNode = {
from("CoherentChip") { inwardNode :=* gen }
}
def fromFrontBus(gen: => TLNode): TLInwardNode = {
from("FrontBus") { master_splitter.node :=* gen }
from("front_bus") { master_splitter.node :=* gen }
}
def fromTile(
@ -104,15 +100,27 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
}
}
def fromCoherentMaster(
name: Option[String] = None,
buffers: Int = 0)
(gen: => TLNode): TLInwardNode = {
from("coherent_master" named name) {
(inwardNode
:=* TLFIFOFixer(TLFIFOFixer.all)
:=* TLBuffer.chain(buffers).reduce(_ :=* _)
:=* gen)
}
}
def fromMaster(
name: Option[String] = None,
buffers: Int = 0)
(gen: => TLNode): TLInwardNode = {
from("master" named name) {
(List(
master_splitter.node,
TLFIFOFixer(TLFIFOFixer.all)) ++
TLBuffer.chain(buffers)).reduce(_ :=* _) :=* gen
(master_splitter.node
:=* TLFIFOFixer(TLFIFOFixer.all)
:=* TLBuffer.chain(buffers).reduce(_ :=* _)
:=* gen)
}
}
}