riscv/rocket-chip
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add config option to trade mul/div area for speed

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This commit is contained in:
Andrew Waterman 2013-01-06 03:47:17 -08:00
parent ce9f4881d2
commit 78868f6075
2 changed files with 4 additions and 2 deletions
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3
rocket/src/main/scala/dpath.scala
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@ -159,7 +159,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
alu.io.in1 := ex_rs1.toUFix alu.io.in1 := ex_rs1.toUFix
// multiplier and divider // multiplier and divider
val div = new MulDiv(mulUnroll = 4, earlyOut = true) val div = new MulDiv(mulUnroll = if (conf.fastMulDiv) 8 else 1,
earlyOut = conf.fastMulDiv)
div.io.req.valid := io.ctrl.div_mul_val div.io.req.valid := io.ctrl.div_mul_val
div.io.req.bits.dw := ex_reg_ctrl_fn_dw div.io.req.bits.dw := ex_reg_ctrl_fn_dw
div.io.req.bits.fn := ex_reg_ctrl_fn_alu div.io.req.bits.fn := ex_reg_ctrl_fn_alu

3
rocket/src/main/scala/tile.scala
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@ -10,7 +10,8 @@ case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached,
icache: ICacheConfig, dcache: DCacheConfig, icache: ICacheConfig, dcache: DCacheConfig,
fpu: Boolean, vec: Boolean, fpu: Boolean, vec: Boolean,
fastLoadWord: Boolean = true, fastLoadWord: Boolean = true,
fastLoadByte: Boolean = false) fastLoadByte: Boolean = false,
fastMulDiv: Boolean = true)
{ {
val dcacheReqTagBits = 9 // enforce compliance with require() val dcacheReqTagBits = 9 // enforce compliance with require()
val xprlen = 64 val xprlen = 64