From 78868f60757d3faa57ab563f6f99d43cbb90f631 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 6 Jan 2013 03:47:17 -0800 Subject: [PATCH] add config option to trade mul/div area for speed --- rocket/src/main/scala/dpath.scala | 3 ++- rocket/src/main/scala/tile.scala | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index ee6630e5..93236aaa 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -159,7 +159,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Component alu.io.in1 := ex_rs1.toUFix // multiplier and divider - val div = new MulDiv(mulUnroll = 4, earlyOut = true) + val div = new MulDiv(mulUnroll = if (conf.fastMulDiv) 8 else 1, + earlyOut = conf.fastMulDiv) div.io.req.valid := io.ctrl.div_mul_val div.io.req.bits.dw := ex_reg_ctrl_fn_dw div.io.req.bits.fn := ex_reg_ctrl_fn_alu diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 55dfc000..1ea180ca 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -10,7 +10,8 @@ case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached, icache: ICacheConfig, dcache: DCacheConfig, fpu: Boolean, vec: Boolean, fastLoadWord: Boolean = true, - fastLoadByte: Boolean = false) + fastLoadByte: Boolean = false, + fastMulDiv: Boolean = true) { val dcacheReqTagBits = 9 // enforce compliance with require() val xprlen = 64